Procedures

Commands

See Also

You can use the Synopsys^® FPGA Express^® design entry/synthesis tool to create, synthesize, and optimize a project and then generate an EDIF Input File (.edf) for compilation in the Quartus^® II software. The following steps describe the typical flow to create, synthesize, and optimize a project, and generate an EDIF Input File:

1. Set up the FPGA Express Working Environment

2. Create a Design for Use with the FPGA Express Software

3. Set Up a Project with the FPGA Express Software

4. Assign Design Constraints and Optimize the Design with the FPGA Express Software

5. Generate EDIF Netlist Files with the FPGA Express Software

6. Analyze Design Results with the FPGA Express Software

You can use Altera-provided megafunctions in EDA tools by using the MegaWizard^® Plug-In Manager (Tools menu) to create custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions. Refer to the following topics for information on how to use specific megafunctions. You can use the same procedures and principles to use similar megafunctions in other designs.

• Creating & Instantiating a Verilog HDL Function for Use with the FPGA Express Software
• Creating & Instantiating a Verilog HDL Function for Use with the FPGA Express and FPGA Compiler II Software
• Creating & Instantiating a VHDL Function for Use with the FPGA Express and FPGA Compiler II Software

More information is available on other EDA design entry/synthesis tools on the Altera® web site.

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