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Assigning design constraints in the Synopsys^® FPGA Express software includes setting global optimization goals and CPU effort designations, and assigning pins, logic options, and timing constraints. You can assign pins, logic options, and timing constraints to a design in Synopsys FPGA Express constraint tables. Some design-specific information is extracted automatically from your design and displayed in the constraint tables; you can also manually make specific assignments in these tables. All design-specific information, such as clock names, port names, and design hierarchy assignments is extracted automatically from the design.

To assign design constraints in the Synopsys FPGA Express software:

1. If you have not already done so, perform 3. Set Up a Project with the FPGA Express Software.

2. To set global optimization controls in the FPGA Express software, perform the following steps:

The Synopsys FPGA Express software allows you to choose either speed or area options and to specify either high, low, or fast CPU effort in logic optimization. Optimization goals are set on a global basis or on particular levels of hierarchy.

1. If you have not already done so, identify the top-level design for your project in the Design Sources window. Select the top-level design from the Identify top-level design list on the toolbar. The Create Implementation dialog box appears.

2. Under Optimize for, select Speed or Area to specify the optimization goal for the entire design:

   • The Speed option minimizes delay by synthesizing circuits to contain the least number of levels of combinatorial logic, sometimes yielding increased design area. This setting maximizes operating frequency and minimizes combinatorial path delays.

   • The Area option minimizes the combinatorial logic resources used, sometimes yielding reduced speed. This setting minimizes combinatorial logic usage.

3. Under Effort, select on High, Low, or Fast to specify the CPU effort level.

   • The Low option increases compilation speed at the expense of larger combinatorial area. This option is most useful for minimizing compilation time for very large designs when neither speed nor area are critical.
   • The High option decreases the combinatorial area at the expense of compilation speed. This option is recommended in speed- or area-critical designs.

   • The Fast option optimizes for both area and effort.

4. If you want to preserve the design hierarchy, turn on Preserve Hierarchy.

5. If you do not want to enter any design constraints, turn on Skip constraint entry.

3. To set optimization goals on a particular level of hierarchy, perform the following steps:

You can set the same optimization controls on individual levels of hierarchy for greater control. This strategy is useful when your design contains hierarchical blocks with different requirements. For example, some blocks may be time-critical while others are not. To obtain the best resuls, you should optimize time-critical blocks for speed and other blocks for area.

1. In the Chips window, expand the preoptimized chip icon.

2. Select the design name, and choose Edit Constraints (right button pop-up menu) to display the constraints tables.

3. Click the Modules tab.

4. Find the row that displays the level of hierarchy for which you want to set an optimization goal.

5. In the Optimize for column, select Speed or Area.

6. In the Effort column, select High, Low, or Fast.

Optimization settings are the same for an entire design file, regardless of its level of hierarchy.

4. To make resource assignments:

1. Select the design implementation icon in the Chips window, choose the Edit Constraints command (right button pop-up menu) to display the Altera-specific constraint tables. These tables allow you to specify resource assignments for your design. All design-specific information such as clock names, port names, and design hierarchy is extracted automatically from the design. Altera^® recommends entering specific requirements directly into these tables to obtain the desired optimization.

2. Make assignments in the appropriate constraint tables. You can click a tab to toggle between tables. Refer to the following table, which shows the available Quartus^® II resource assignment options in the FPGA Express constraint tables. The Clock and Paths tabs already contain information that you previously entered in the Create Implementation dialog box.

   Quartus II Resource Assignments in FPGA Express Constraint Tables

   Quartus II Resource Assignment	Equivalent FPGA Express Constraint Table Setting
   	Tab Name	Action
   Pin assignment	Ports	Specify the pin number in the Pad Loc column.
   tSU timing assignment	Ports	Specify the time in the Input Delay column.
   tCO timing assignment	Ports	Specify the time in the Output Delay column.
   Slow Slew Rate logic option assignment	Ports	Click the appropriate cell in the Slew Rate column and select <default>, FAST, or SLOW from the list.
   Fast I/O logic option assignment	Ports	Click the appropriate cell in the Use I/O Reg column and select <default>, ON, or OFF in the list.
   tPD timing assignment	Paths	Specify the time in the Req. Delay column.

3. Close the window and click Yes to save the changes to the constraint table.

5. To optimize the design, select the design implementation icon in the Project window and click the Optimize button on the toolbar. A new optimized implementation icon appears beneath the original implementation icon. When you open the optimized implementation, the constraint tables are back-annotated with the optimization results. The FPGA Express software optimizes a design for either speed or area.

6. To continue with the FPGA Express design flow, proceed to one of the following steps:

   • 5. Generate EDIF Netlist Files with the FPGA Express^® Software
   • 6. Analyze Design Results with the FPGA Express Software

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