EDA Interfaces

2. Create a Design for Use with the FPGA Express Software



You can create VHDL and Verilog HDL design files with the Quartus® II Text Editor or another standard text editor for use with the Synopsys® FPGA Express software.

To create a Verilog HDL or VHDL design for use with the FPGA Express software:

  1. If you have not already done so, perform 1. Set Up the FPGA Express Working Environment.

  2. Enter a VHDL or Verilog HDL design in the Quartus II Text Editor or another standard text editor and save it in your working directory.

  3. Describe your design using FPGA Express-supported Verilog HDL or VHDL constructs. For information on synthesizable Verilog HDL or VHDL constructs, refer to the online HDL Reference Manual provided with the FPGA Express software. The Quartus II software supports all LPM functions except the truth table, finite state machine, and pad functions. The FPGA Express software supports all LPM megafunctions that are supported in the Quartus II software except the lpm_and, lpm_or, lpm_xor, and lpm_mux functions.

  4. To use megafunctions in the design, use the MegaWizard® Plug-In Manager (Tools menu) to generate and instantiate a megafunction variation. You can use the MegaWizard Plug-In Manager to create content-addressable memory (CAM), ClockLock® PLL, LVDS, and RAM functions. The following topics show how to create and instantiate some of these functions.


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