32-bit DSP processor

synthesisable version with COMPASS ASIC synthetizer

prepared by P. Bakowski (designer K. Djigande)

This processor design is described (in french). click here

The synthesisable 32-bit version is built from several modules.

The main module contains the declaration of the internal components used to build the whole processor.

Each module is synthesised separately.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

use work.tms8.all;

entity mon_ens32 is

Port(nRS,clk,nbio:in std_logic; DBUS:in BIT32; ABUS:out BIT12; MEN:out std_logic; d_bus:out BIT32; h_imp:inout std_logic; nWE:out std_logic; nDEN:out std_logic );

end mon_ens32;

architecture beh_mon_ens of mon_ens32 is

component horl_p port(reset,clk:in std_logic; H:out std_logic );

end component;

component fetch32_p port(clk,reset:in std_logic; succes:in boolean; accu:in BIT64; MEN:out std_logic; PC:out BIT12; stackP:out BIT12; InstReg:in BIT32);

end component;

component mem32_p port(InstReg:in BIT32; AR0,AR1:in BIT32; reset,clk,DataP,ARP:in std_logic; addr_R,addr_W:out BIT8; InstReg0:out BIT32; Rd,lect:out std_logic; nDEN:out std_logic);

end component;

component gest_ram32_p port(H,clk,Rd,Wt:in std_logic; ad_ram_e,ad_ram_l:in BIT8; data_out:out BIT32; data_in:in BIT32);

end component;

component mon_alu32_p port(oper:in BIT3; operand1,operand2:in BIT64; ovm,setov,ovfl:in std_logic; ov:out std_logic; result:out BIT64);

end component;

component mult32_p port (a,b:in BIT32; outlow,outhigh:BIT32);

end component;

component execution32_p port(InstReg1:in BIT32; data_in:in BIT32; vers_data:out BIT32; mult_e1,mult_e2:out BIT32; InstReg2:out BIT32; AR0s,AR1s:out BIT32; reset,clk,lect,bio,ov:in std_logic; alu_ope:out BIT3; alu_e1,alu_e2:out BIT64; accu,P:in BIT64; stackP:in BIT12; succes:out boolean; nWE,DataPs,ARPs,intms,ovms,setov,ovfl:out std_logic; h_imp:inout std_logic; d_bus:out BIT32 );

end component;

component part2_32_p port(InstReg2:in BIT32; vers_data:in BIT32; dataW:out BIT32; addr_e:out BIT8; addr_W:in BIT8; reset,clk:in std_logic; Wt:out std_logic );

end component;

component gene_reset_p port(nRS,clk:in std_logic;reset:out std_logic);

end component;

for all:horl_p use entity work.horl_p(horl_p);

for all:fetch32_p use entity work.fetch32_p(fetch32_p);

for all:mem32_p use entity work.mem32_p(mem32_p);

for all:gest_ram32_p use entity work.gest_ram32_p(gest_ram32_p);

for all:execution32_p use entity work.execution32_p(execution32_p);

for all:mon_alu32_p use entity work.mon_alu32_p(mon_alu32_p);

for all:mult32_p use entity work.mult32_p(mult32_p);

for all:part2_32_p use entity work.part2_32_p(part2_32_p);

for all:gene_reset_p use entity work.gene_reset_p(gene_reset_p);

signal iRd,iWt,ilect,iDataP,iARP,ireset,iH:std_logic;

signal isucces:boolean;

signal iInstReg0,iInstReg2:BIT32;

signal iAR0,iAR1,imult_e1,imult_e2:BIT32;

signal ivers_data,id_ram,idataW:BIT32;

signal ioper:BIT3; signal istackP:BIT12;

signal iaddr_R,iaddr_W,iaddr_e:BIT8;

signal ialu_e1,ialu_e2,iaccu,iP:BIT64;

signal iovm,isetov,iovfl,iov,iintm: std_logic;

begin

u0:horl_p port map(reset=>ireset,clk=>clk,H=>iH);

u1:fetch32_p port map(clk=>iH,reset=>ireset,succes=>isucces, accu=>iaccu,stackP=>istackP,MEN=>MEN,PC=>ABUS,InstReg=>DBUS);

u2:mem32_p port map(InstReg=>DBUS,AR0=>iAR0,AR1=>iAR1, reset=>ireset,clk=>iH,DataP=>iDataP,ARP=>iARP, addr_R=>iaddr_R,addr_W=>iaddr_W,InstReg0=>iInstReg0, Rd=>iRd,lect=>ilect,nDEN=>nDEN);

u3:gest_ram32_p port map(H=>iH,clk=>clk,Rd=>iRd,Wt=>iWt,ad_ram_e=>iaddr_e, ad_ram_l=>iaddr_R,data_out=>id_ram,data_in=>idataW);

u4:mon_alu32_p port map(oper=>ioper,operand1=>ialu_e1,operand2=>ialu_e2, ovm=>iovm,setov=>isetov,ovfl=>iovfl,ov=>iov, result=>iaccu);

u5:mult32_p port map(a=>imult_e1,b=>imult_e2, outlow=>iP(31 downto 0),outhigh=>iP(63 downto 32));

u7:execution32_p port map(InstReg1=>iInstReg0,data_in=>id_ram, vers_data=>ivers_data, mult_e1=>imult_e1,mult_e2=>imult_e2, InstReg2=>iInstReg2,AR0s=>iAR0,AR1s=>iAR1, reset=>ireset,clk=>iH,lect=>ilect, bio=>nbio,ov=>iov,alu_ope=>ioper, alu_e1=>ialu_e1,alu_e2=>ialu_e2,accu=>iaccu,P=>iP, stackP=>istackP, succes=>isucces,nWE=>nWE,DataPs=>iDataP,ARPs=>iARP, intms=>iintm,ovms=>iovm,setov=>isetov, ovfl=>iovfl,h_imp=>h_imp, d_bus=>d_bus);

u9:part2_32_p port map(InstReg2=>iInstReg2,vers_data=>ivers_data, dataW=>idataW,addr_e=>iaddr_e,addr_W=>iaddr_W, reset=>ireset,clk=>iH,Wt=>iWt); u10:gene_reset_p port map(nRS=>nRS,clk=>clk,reset=>ireset);

End beh_mon_ens;