ALU module
synthesisable desription with COMPASS ASIC synthetizer
prepared by P. Bakowski (designer K. Djigande)
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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY COMPASS_LIB;
USE COMPASS_LIB.COMPASS.ALL;
use work.tms8.all;
entity mon_alu32 is
port(oper:in BIT3; operand1,operand2:in BIT64; ovm,setov,ovfl:in
std_logic; ov:out std_logic; result:out BIT64);
end mon_alu32;
architecture beh_mon_alu32 of mon_alu32 is
begin
process(oper,operand1,operand2,ovm,setov,ovfl)
variable res:BIT64;
begin
case oper is
when "111"=> res:=operand1 xor operand2;
when "110"=> res:=operand1 and operand2;
when "101"=> res:=operand1 or operand2;
when "100"=> res:=operand1 + operand2;
when "011"=> res:=operand1 - operand2;
when "010"=> res:=operand2;
when others=> res:=extend("0",64);
end case;
if setov='1' then
ov<=ovfl;
elsif ((not(res(63)=operand1(63)) and not(res(63)=operand2(63))
and oper="100") or (not(operand1(63)=operand2(63)) and res(63)='0'
and oper="011")) then
ov<='1';
else ov<='0';
end if;
if ((not(res(63)=operand1(63)) and not(res(63)=operand2(63)) and
oper="100") or (not(operand1(63)=operand2(63)) and oper="011"))
and (ovm='1') then
if (res(63)='1') then result(62 downto 0)<=sign_extend("1",63);
else result(62 downto 0)<=extend("0",63);
end if;
result(63)<=not(res(63));
else
result(63 downto 0)<=res(63 downto 0);
end if;
end process;
end beh_mon_alu32;
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