Reset module
synthetisable description
prepared by P. Bakowski (designer K. Djigande)
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY COMPASS_LIB;
USE COMPASS_LIB.COMPASS.ALL;
entity gene_reset is
port(nRS,clk:in std_logic;reset:out std_logic);
end gene_reset;
architecture beh_gene_reset of gene_reset is
begin
process(nRS,clk)
variable i:integer range 0 to 5;
begin
if nRS='1' then
reset<='0';i:=0;
elsif clk'event and clk='1' then
if i=4 then
reset<='1';
end if;
if i<5 then
i:=i+1;
end if;
end if;
end process;
end beh_gene_reset;
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