Fetch module
prepared by P. Bakowski (designer K. Djigande)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY COMPASS_LIB;
USE COMPASS_LIB.COMPASS.ALL;
use work.tms8.all;
entity fetch32 is
port(clk,reset:in std_logic; succes:in boolean; accu:in BIT64;
MEN:out std_logic; PC:out BIT12; stackP:out BIT12; InstReg:in BIT32);
end fetch32;
architecture beh_fetch32 of fetch32 is
signal iMEN,ret,jump,tblr1:std_logic;
signal stack_p:BIT2;
signal vpc:BIT12;
signal IR_old:BIT32;
signal temoin:std_logic;
signal stack1,stack2,stack3,stack0:BIT12;
begin
MEN<=iMEN;
stackP<=stack0 when stack_p="00"
else stack1 when stack_p="01"
else stack2 when stack_p="10"
else stack3;
PC<=vpc when iMEN='1'
else vpc(11 downto 3)&InstReg(10 downto 8);
princ: process(clk,reset)
begin
if reset='1' then
vpc<="000000000000"; iMEN<='1';temoin<='1';
IR_old<=extend("0111111110000000",32);ret<='0';jump<='0';
stack3<="000000000000";stack2<="000000000000";
stack1<="000000000000";stack0<="000000000000";
tblr1<='0';
elsif clk'event and clk='0' then
if IR_old(15 downto 8)="01100111" and tblr1='1' and temoin='1'
then
case stack_p is
when "11" =>vpc<=stack2 + "000000000001";
when "10" =>vpc<=stack1 + "000000000001";
when "01" =>vpc<=stack0 + "000000000001";
when "00" =>vpc<=stack3 + "000000000001";
end case;
ret<='1';jump<='0';tblr1<='0';
elsif IR_old(15 downto 12)="1111" and succes and temoin='1'
then
ret<='0';
if not(IR_old(11 downto 8)="1000") then
jump<='0';
else
case stack_p is
when "11" => stack3<=vpc;
when "10" => stack2<=vpc;
when "01" => stack1<=vpc;
when "00" =>stack0<=vpc;
end case; jump<='1';
end if;
vpc(11 downto 0)<=InstReg(11 downto 0);
elsif InstReg=extend("0111111110001100",32) and temoin='1'
then
--CALA
case stack_p is
when "11" => stack3<=vpc;
when "10" => stack2<=vpc;
when "01" => stack1<=vpc;
when "00" =>stack0<=vpc;
end case;
jump<='1';ret<='0'; vpc(11 downto 0)<=accu(11 downto 0);
elsif InstReg=extend("0111111110011100",32) and temoin='1'
then
--PUSH
ase stack_p is
when "11" => stack3(11 downto 0)<=accu(11 downto
0); when "10" => stack2(11 downto 0)<=accu(11 downto 0);
when "01" => stack1(11 downto 0)<=accu(11 downto
0); when "00" => stack0(11 downto 0)<=accu(11 downto 0);
end case;
jump<='1';ret<='0'; vpc<=vpc + extend("1",12);
elsif InstReg(15 downto 8)="01100111" and temoin='1'
then
--tblr
case stack_p is
when "11" => stack3<=vpc;
when "10" => stack2<=vpc;
when "01" => stack1<=vpc;
when "00" => stack0<=vpc;
end case;
jump<='1';ret<='0';tblr1<='1'; vpc(11 downto 0)<=accu(11
downto 0);
elsif InstReg=extend("0111111110001101",32) and temoin='1'
then
--RET
case stack_p is
when "11" =>vpc<=stack2 + "000000000001";
when "10" =>vpc<=stack1 + "000000000001";
when "01" =>vpc<=stack0 + "000000000001";
when "00" =>vpc<=stack3 + "000000000001";
end case; ret<='1';jump<='0';
else ret<='0';jump<='0';
if not(InstReg(15 downto 12)="0100" and temoin='1' and
tblr1='0') then v
pc<=vpc + extend("1",12);
end if;
end if;
if (temoin='0' or tblr1='1') then
IR_old<=extend("0111111110000000",32);
else IR_old<=InstReg;
end if;
if (InstReg(15 downto 12)="0100" and temoin='1' and tblr1='0')
then
iMEN<='0';temoin<='0';
else iMEN<='1';temoin<='1';
end if; end if;
end process princ;
PP:process(reset,clk)
begin
if reset='1' then
stack_p<="00";
elsif clk'event and clk='1' then
if jump='1' then
inc2(stack_p);
elsif ret='1' then
dec2(stack_p);
end if; end if;
end process PP;
end beh_fetch32;
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