Specific
instructions module
synthetisable description
prepared by P. Bakowski (designer K. Djigande)
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY COMPASS_LIB;
USE COMPASS_LIB.COMPASS.ALL;
use work.tms8.all;
entity part2_32 is
port(InstReg2:in BIT32; vers_data:in BIT32; dataW:out BIT32; addr_e:out
BIT8; addr_W:in BIT8; reset,clk:in std_logic; Wt:out std_logic );
end part2_32;
architecture beh_part2_32 of part2_32 is
signal tblr,Ent_sort,inp:std_logic;
begin
process(clk,reset)
begin if reset='1' then
Wt<='0';tblr<='0';inp<='0'; dataW<=extend("0",32);
addr_e<="10001111";Ent_sort<='0';
elsif clk'event and clk='1' then
if Ent_sort='1' and inp='1' then
dataW<=InstReg2;addr_e<=addr_W;Wt<='1';
elsif ( InstReg2(15 downto 12)="0101" or
--SACHL
InstReg2(15 downto 8)="01101011" or
--LTD
InstReg2(15 downto 11)="00110" or
--SAR
InstReg2(15 downto 8)="01111100" or
--SST
InstReg2(15 downto 8)="01101001")
--DMOV
and Ent_sort='0' and tblr='0' then
dataW<=vers_data; addr_e<=addr_W;Wt<='1';
elsif tblr='1' then
Wt<='1';
--TBLR
addr_e<=addr_W;dataW<=InstReg2; else Wt<='0';
end if;
if InstReg2(15 downto 12)="0100" and tblr='0' and Ent_sort='0'
then
Ent_sort<='1'; if InstReg2(11)='0' then
inp<='1';else inp<='0';
end if;
else Ent_sort<='0';inp<='0';
end if;
if InstReg2(15 downto 8)="01100111" and Ent_sort='0'
and tblr='0' then
tblr<='1';
else tblr<='0';
end if;
end if;
end process;
end beh_part2_32;
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