Clock module
prepared by P. Bakowski (designer K. Djigande)
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
LIBRARY COMPASS_LIB;
use COMPASS_LIB.compass.all;
entity horl is
port(reset,clk:in std_logic; H:out std_logic);
end horl;
architecture beh_horl of horl is
signal S:std_logic;
begin
H<=S;
process(reset,clk)
begin
if reset='1' then
S<='1';
elsif clk'event and clk='1' then
if S='1' then
S<='0';
else S<='1';
end if;
end if;
end process;
end beh_horl;
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