Execution
module
synthesisable description with COMPASS ASIC synthesizer
prepared by P. Bakowski (designer K. Djigande)
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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY COMPASS_LIB;
USE COMPASS_LIB.COMPASS.ALL;
USE COMPASS_LIB.compass_arith.ALL;
use work.tms8.all;
entity execution32 is
port(InstReg1:in BIT32; data_in:in BIT32; vers_data:out BIT32;
mult_e1,mult_e2:out BIT32; InstReg2:out BIT32; AR0s,AR1s:out BIT32; reset,clk,lect,bio,ov:in
std_logic; alu_ope:out BIT3; alu_e1,alu_e2:out BIT64; accu,P:in BIT64;
stackP:in BIT12; succes:out boolean; nWE,DataPs,ARPs,intms,ovms,setov,ovfl:out
std_logic; h_imp:inout std_logic; d_bus:out BIT32 );
End execution32;
architecture beh_execution32 of execution32 is
signal T,AR0,AR1:BIT32;
signal drap_accu:BIT2;
signal ARP,DataP,ovm,intm:std_logic;
begin
AR0s<=AR0;AR1s<=AR1;ARPs<=ARP; DataPs<=DataP;intms<=intm;ovms<=ovm;
ph1_inst_dec:
process(clk,reset)
variable v_sh:BIT4;
variable donnee:BIT32;
variable saut,Ent_sort:boolean;
variable long,var_accu:BIT64;
begin
if reset='1' then
ARP<='0';DataP<='0';nWE<='1';ovfl<='0'; succes<=false;intm<='0';ovm<='0';setov<='0';
Ent_sort:=false; AR0<=extend("0",32);AR1<=extend("0",32);
vers_data<=extend("0",32);mult_e1<=extend("0",32);
mult_e2<=extend("0",32);instReg2<=extend("0111111110000000",32);
alu_e1<=extend("0",64); alu_e2<=extend("0",64);
alu_ope<="000"; d_bus<=extend("0111111110000000",32);h_imp<='1';
T<=extend("0",32); v_sh:="0000"; donnee:=extend("0",32);saut:=false;
var_accu:=extend("0",64); long:=extend("0",64);
elsif clk'event and clk='1' then
if InstReg1(15 downto 11)="01001" and h_imp='1' then
h_imp<='0';
else H_imp<='1';
end if;
if not(Ent_sort) then
if (lect='1' and InstReg1(7)='1' and not(InstReg1(15 downto 12)="0011"))
then
if (InstReg1(5)='1' and InstReg1(4)='0') then
if ARP='1' then
AR1<=AR1+'1';
elsif ARP='0' then
AR0<=AR0+'1';
end if;
elsif (InstReg1(5)='0' and InstReg1(4)='1') then
if ARP='1' then AR1<=AR1-'1';
elsif ARP='0' then
AR0<=AR0-'1';e
nd if;
end if;
if InstReg1(3)='0' then
ARP<=InstReg1(0);end if;
end if;
if InstReg1(15 downto 11)="01000" then
--IN --
vers_data<=DBUS; nWE<='1';
elsif InstReg1(15 downto 11)="01001" then
--OUT
d_bus<=data_in;nWE<='0';
else nWE<='1';
end if;
case InstReg1(15 downto 12) is
when "1111" => --branch
case InstReg1(11 downto 8) is
when "0110" => --BIOZ
succes<=(bio='0');
when "1100" => --BGZ
succes<=(drap_accu="10");
when "1101" => --BGEZ
succes<=not(drap_accu="01");
when "1010" => --BLZ
succes<=(drap_accu="01");
when "1011" => --BLEZ
succes<=not(drap_accu="10");
when "1110" => --BNZ
succes<=not(drap_accu="00");
when "1111" => --BZ
succes<=(drap_accu="00");
when "0101" => --BV
succes<=(ov='1'); if (ov='1') then
setov<='1';ovfl<='0';
else setov<='0';
end if;
when "1001" | "1000" => succes<=true;
when "0100" => if ARP='1' then
succes<=not(AR1=extend("0",32));
if not(AR1=extend("0",32)) then
donnee:=AR1-'1'; AR1<=donnee;
end if;
else
succes<=not(AR0=extend("0",32));
if not(AR0=extend("0",32)) then
donnee:=AR0-'1'; AR0<=donnee;
end if; end if;
when
others =>succes<=false;
end case;
when "0001" | "0000" => --arith
if not(saut) then
v_sh(3 downto 0):=InstReg1(11 downto 8); donnee:=data_in; alu_e2<=bshl32(v_sh,donnee);
alu_e1<=accu;
if InstReg1(12)='0' then
alu_ope<="100";
else alu_ope<="011";
end if;
end if;
when "0101" => --SACHL
v_sh(2 downto 0):=InstReg1(10 downto 8); v_sh(3):='0'; var_accu:=accu;
if InstReg1(11)='1' then
pshl32(v_sh,var_accu); vers_data(7 downto 0)<=var_accu(15 downto
8);
else vers_data(31 downto 0)<=var_accu(31 downto 0);
end if;
when "0111" => --large
if InstReg1(11 downto 8)="1111" then --immed
case InstReg1(7 downto 0) is
when "10001100" => --CALA
null;
when "10000001" => --DINT
intm<='1';
when "10000010" => --EINT
intm<='0';
when "10001010" => --ROVM
ovm<='0';
when "10001011" =>
--SOVM
ovm<='1';
when "10011101" => --POP
alu_e2(11 downto 0)<=stackP(11 downto 0); alu_ope<="010";
when "10001001" => --ZAC
alu_ope<="001";
when "10001000" => --ABS
alu_e2<=val_abs32(accu);alu_ope<="010";
when "10001110" => alu_ope<="010";--PAC
alu_e2<=P;alu_e1<=accu;
when "10001111" => alu_ope<="100";--APAC
alu_e2<=P;alu_e1<=accu;
when "10010000" => alu_ope<="011";--SPAC
alu_e2<=P;alu_e1<=accu;
when others => null;
end case;
elsif InstReg1(11 downto 8)="1110" then --LACK
alu_e2(7 downto 0)<=InstReg1(7 downto 0); alu_e2(63 downto 8)<=extend("0",56);
alu_ope<="010";
elsif InstReg1(11 downto 8)="1011" then --lst
ovm<=data_in(6);intm<=data_in(5); ovfl<=data_in(7);setov<='1';
ARP<=data_in(4);DataP<=data_in(0);
elsif InstReg1(11 downto 8)="1100" then --sst
vers_data(3 downto 1)<="111";vers_data(0)<=DataP;
vers_data(4)<=ARP; vers_data(7)<=ov;vers_data(6)<=ovm;vers_data(5)<=intm;
elsif InstReg1(11)='0' then --lark
if InstReg1(8)='1' then AR1(7 downto 0)<=InstReg1(7 downto 0);
else AR0(7 downto 0)<=InstReg1(7 downto 0);
end if;
elsif (InstReg1(11 downto 10)="10") then --logique
alu_e2(31 downto 0)<=data_in(31 downto 0); alu_e2(63 downto
32)<=extend("0",32); alu_e1<=accu;
if InstReg1(9)='0' then
if InstReg1(8)='1' then
alu_ope<="110";
else alu_ope<="111";
end if;
else
if InstReg1(8)='0' then
alu_ope<="101";
end if;
end if;
end if;
when "0110" => --cherch
case InstReg1(11 downto 8) is
when "1110" => --LDPK DataP<=InstReg1(0);
when "0001" => alu_e2(31 downto 0)<=data_in(31
downto 0); alu_e2(63 downto 32)<=extend("0",32); alu_e1<=accu;
alu_ope<="100";
when "0000" => alu_e2(31 downto 0)<=extend("0",32);
alu_e2(63 downto 32)<=data_in(31 downto 0); alu_e1<=accu; alu_ope<="100";
when "0011" => alu_e2(31 downto 0)<=data_in(31
downto 0); alu_e2(63 downto 32)<=extend("0",32); alu_e1<=accu;
alu_ope<="011";
when "0010" => alu_e2(31 downto 0)<=extend("0",32);
alu_e2(63 downto 32)<=data_in(31 downto 0); alu_e1<=accu; alu_ope<="011";
when "0100" => --SUBC var_accu:=accu; long:=extend(data_in,64);
shl31(long); subc32(var_accu,long); alu_e1<=var_accu;alu_e2<=long;alu_ope<="100";
when "0101" => --ZALH
alu_e2(31 downto 0)<=extend("0",32); alu_e2(63 downto
32)<=data_in(31 downto 0); alu_ope<="010";
when "0110" => alu_e2(63 downto 32)<=extend("0",32);
alu_e2(31 downto 0)<=data_in(31 downto 0); alu_ope<="010";
when "1111" => --LDP
DataP<=data_in(0);
when "1001" => --DMOV
vers_data<=data_in;
when "1101" => --MPY
mult_e1<=T;mult_e2<=data_in;
when "1010" => --LT
T<=data_in;
when "1100" => --LTA
T<=data_in; alu_e1<=accu;alu_e2<=P;alu_ope<="100";
when "1011" => --LTD
T<=data_in; vers_data<=data_in; alu_e1<=accu;alu_e2<=P;alu_ope<="100";
when "1000" => --LARP
if (InstReg1(11 downto 1)="10001000000") then
ARP<=InstReg1(0);
end if;
when others => null;
end case;
when "1001" | "1000" => --MPYK
mult_e2<=sign_extend(InstReg1(12 downto 0),32); mult_e1<=T;
when "0011" => --LAR
if InstReg1(11)='1' then
if InstReg1(8)='1' then
AR1<=data_in;
else AR0<=data_in;
end if;
else --SAR
if InstReg1(8)='0' then
vers_data<=AR0;
else vers_data<=AR1;
end if;
end if;
when "0010" => --LAC
v_sh(3 downto 0):=InstReg1(11 downto 8); donnee:=data_in; alu_e2<=bshl32(v_sh,donnee);
alu_e1<=accu;alu_ope<="010";
when others => null;
end case;
saut:=(InstReg1(15 downto 12)="1111");
else nWE<='1';
end if;
InstReg2<=InstReg1;
if (InstReg1(15 downto 12)="0100" or InstReg1(15 downto
8)="01100111") and not(Ent_sort) then
Ent_sort:=true;
else
Ent_sort:=false;
end if;
if not(InstReg1(15 downto 8)="01111011" or InstReg1(15
downto 8)="11110101") then
setov<='0';end if;--lst end if; end process ph1_inst_dec;
flag_accu:process(accu)
begin if accu(63)='1' then
drap_accu<="01"; else if accu=extend("0",64)
then
drap_accu<="00";
else drap_accu<="10";
end if;
end if;
end process flag_accu;
end beh_execution32;
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