Memory control for tms32

Internal memory component and control

prepared by P. Bakowski (designer K. Djigande)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY COMPASS_LIB;

USE COMPASS_LIB.COMPASS.ALL;

use work.tms8.all;

entity gest_ram32 is

port(H,clk,Rd,Wt:in std_logic; ad_ram_e,ad_ram_l:in BIT8; data_out:out BIT32; data_in:in BIT32);

end gest_ram32;

architecture beh_gest_ram32 of gest_ram32 is

component gr32_p

port(H,Rd,Wt:in std_logic; ad_ram_e,ad_ram_l:in BIT8; WEB,OEB:out std_logic; A:out BIT8; d_in:out BIT32; data_in:in BIT32);

end component;

component la_ram32

port(WEB,OEB:in std_logic; d_in:in BIT32; CEB:in std_logic; A:in BIT8; d_out:out BIT32);

end component;

for all:la_ram32 use entity work.la_ram32(beh_la_ram32);

for all:gr32_p use entity work.gr32_p(gr32_p);

signal iWEB,iOEB:std_logic;

signal id_in:BIT32;

signal iA:BIT8;

begin

u1:gr32_p port map(H=>H,Rd=>Rd,Wt=>Wt, ad_ram_e=>ad_ram_e, ad_ram_l=>ad_ram_l, WEB=>iWEB,OEB=>iOEB, A=>iA,d_in=>id_in, data_in=>data_in );

u2:la_ram32 port map(WEB=>iWEB,OEB=>iOEB, d_in=>id_in,CEB=>clk, A=>iA,d_out=>data_out);

end beh_gest_ram32;