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Not all primitives/ports may connect to all other primitives in a design file. The following lists show the possible interconnections for all primitives/ports except logic and WIRE primitives:
| Source |
Destination |
|||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Primitive | ||||||||||
| OUTPUT/ OUT |
BIDIR/ INOUT |
TRI Note (1) | GLOBAL | ROW_GLOBAL | LCELL | EXP | SOFT | Logic | INPUT/ IN Note (2) |
|
INPUT
or IN |
Y | N | Y | Y | Y | na | na | na | Y | Y |
OUTPUT
or OUT
Note (3) |
N | N | N | N | N | N | N | N | N | N |
BIDIR
or INOUT
Note (3) |
N | N | Y | N | N | na | na | na | Y | Y |
TRI |
Y | Y | Note (4) | na | na | Note (4) | Note (4) | Note (4) | Note (4) | Note (4) |
OPNDRN |
Y | Y | Note (4) | na | na | Note (4) | Note (4) | Note (4) | Note (4) | Note (4) |
GLOBAL |
na | N | Note (5) | Y | Y | na | na | na | na | na |
LCELL |
Y | N | Y | Y | Y | na | na | na | Y | na |
EXP |
na | N | na | Y | Y | na | na | na | Y | na |
SOFT |
Y | N | na | Y | Y | na | na | na | Y | na |
VCC |
Y | N | Y | N | N | na | na | na | Y | N |
GND |
Y | N | Y | N | N | na | na | na | Y | N |
| Logic | Y | N | Y | Y | Y | Y | Y | Y | Y | Y |
| Reg Out | Y | N | Y | Y | Y | na | na | Y | Y | Y |
CARRY |
na | na | na | N | N | Y | na | na | Y | na |
CASCADE |
na | na | na | N | N | na | na | na | Y | na |
|
Source |
Destination |
||||||||
|---|---|---|---|---|---|---|---|---|---|
|
Primitive |
Register Port |
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| CARRY | CASCADE | OPNDRN | CLK | PRN | CLRN | ||||
| na | na | Y | Y | Y | Y | ||||
OUTPUT
or OUT
Note (3) |
na | na | N | N | N | N | |||
BIDIR
or INOUT
Note (3) |
na | na | Y | Y | Y | Y | |||
TRI |
na | na | Note (4) | Note (4) | Note (4) | Note (4) | |||
OPNDRN |
na | na | Note (4) | Note (4) | Note (4) | Note (4) | |||
GLOBAL |
Y | na | na | Y | Y | Y | |||
ROW_GLOBAL |
Y | na | na | Y | Y | Y | |||
LCELL |
na | na | Y | Y | Y | Y | |||
EXP |
na | na | na | na | na | na | |||
SOFT |
na | na | na | Y | Y | Y | |||
VCC |
na | na | Y | N | Y | Y | |||
GND |
na | na | Y | N | Y | Y | |||
| Logic | Y | Y | Y | Y | Y | Y | |||
| Reg Out | na | na | Y | Y | Y | Y | |||
CARRY |
na | na | na | na | na | na | |||
CASCADE |
na | na | na | na | na | na | |||
Legend:
| Y | Interconnection is legal. |
| N | Interconnection is illegal. |
| na | Interconnection is legal but not advisable or may implement logic inefficiently. |
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- PLDWorld - |
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