Primitive

ROW_GLOBAL Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION ROW_GLOBAL (in)
   RETURNS (out);


VHDL Component Declaration:

COMPONENT ROW_GLOBAL
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;

The ROW_GLOBAL buffer indicates that a signal must use a global (synchronous) clock, clear, preset, output enable, or write enable signal. Row-global signals are used in the Mercury device family according to row-global signal availability.

If an input pin (or a logic function) feeds directly to the input of ROW_GLOBAL, the output of ROW_GLOBAL can be used to feed a clock, clear, preset, output enable, or write enable input to a primitive. A direct connection must exist from the output of ROW_GLOBAL to the input of the register or the TRI buffer.

Row-global signals propagate more quickly than array signals and may free up device resources for other logic. ROW_GLOBAL should be used to implement global clocking in a portion or all of the project. To verify that registers are globally clocked, you can refer to the Text-Format Report File (.rpt) or HTML-Format Report File (.htm) for the processed project.

As an alternative to using the ROW_GLOBAL primitive, you can also make a pin or internal logic into a row-global signal by selecting it and turning on the Row Global Signal logic option. When you turn on the Ignore ROW GLOBAL Buffers logic option, the Compiler converts all ROW_GLOBAL buffers to WIRE primitives.


Back to Top

- PLDWorld -

 

Created by chm2web html help conversion utility.