Primitive

CASCADE Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION CASCADE (in)
   RETURNS (out);


VHDL Component Declaration:

COMPONENT CASCADE
   PORT (a_in : IN STD_LOGIC;
     a_out: OUT STD_LOGIC);
END COMPONENT;

The CASCADE buffer designates the cascade-out function from an AND or OR gate, and acts as a cascade-in to another AND or OR gate. The cascade-in function allows a cascade, which is a fast output located on each combinatorial logic cell, to be ORed or ANDed with the output of an adjacent combinatorial logic cell in the device. When you use a CASCADE primitive, the AND or OR gate that feeds the CASCADE primitive and the AND or OR gate that is fed by the CASCADE primitive are placed in the device, with the first symbol logically ORed or ANDed into the second.


NOTE The CASCADE primitive is not supported for Cyclone, MAX® 3000, MAX 7000, Mercury, Stratix, or Stratix GX devices. In FLEX® 6000 devices the Quartus® II software never assigns the starting point of a cascade chain to the first logic cell (LC1) in a LAB.

When you use a CASCADE primitive, you must observe the following rules:

If you use the CASCADE primitive incorrectly, it is ignored and the Compiler issues a warning.

When you turn on the Automatic Cascade Chains logic option, the Compiler automatically inserts CASCADE primitives during logic synthesis. When you turn on the Ignore CASCADE Buffers logic option, the Compiler converts all CASCADE buffers to WIRE primitives.


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