Primitive

CARRY Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION CARRY (in)
   RETURNS (out);


VHDL Component Declaration:

COMPONENT CARRY
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;
NOTE The CARRY primitive is provided only for backward compatibility with MAX+PLUS® II designs. New projects should use CARRY_SUM exclusively.

The CARRY primitive designates the carry-out logic for a function, and acts as the carry-in to another function. The carry function implements fast carry-chain logic for functions such as adders and counters.

NOTE The CARRY primitive is not supported for MAX® 3000 or MAX 7000 devices. In APEX 20K, APEX II, and ARM®-based Excalibur, devices the Quartus® II software assigns the starting point of a counter to the first logic cell (LC1) in a Logic Array Block (LAB); non-counter carry chains can start in any logic cell. In FLEX® 6000 devices the Quartus II software assigns the starting point of a counter to the second logic cell (LC2) in a LAB; carry chains can start in any logic cell except LC1.

When you use a CARRY primitive, you must observe the following rules:

If you use the CARRY primitive incorrectly, it is ignored and the Compiler issues a warning.


NOTE If you have a CARRY buffer in the design, you must turn on the Auto Carry Chains logic option. When it is turned off, any CARRY buffer is ignored. CARRY_SUM buffers are not affected. If you turn on the Auto Carry Chains logic option and the Compiler does not recognize the CARRY buffer, use the CARRY_SUM buffer.

When you turn on the Ignore CARRY Buffers logic option, the Compiler automatically converts all CARRY buffers to wires.


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