Primitive

SOFT Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION SOFT (in)
   RETURNS (out);


VHDL Component Declaration:

COMPONENT SOFT
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;

The SOFT buffer specifies that a logic cell may be needed in the project. During project processing, the Logic Synthesizer examines the logic feeding the primitive and determines whether a logic cell is needed. If it is needed, the SOFT buffer is converted into an LCELL; if not, the SOFT buffer is removed.

If the Compiler indicates that the project is too complex, you can edit the project by inserting SOFT buffers to prevent logic expansion. For example, you can add a SOFT buffer at the combinatorial output of a logic function to decouple two combinatorial circuits.

When you turn on the Ignore SOFT Buffers logic option, the Compiler automatically converts all SOFT buffers to WIRE primitives.


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