Primitive

GLOBAL Primitive



AHDL Function Prototype (port name and order also apply to Verilog HDL):

FUNCTION GLOBAL (in)
   RETURNS (out);


VHDL Component Declaration:

COMPONENT GLOBAL
   PORT (a_in : IN STD_LOGIC;
      a_out: OUT STD_LOGIC);
END COMPONENT;

The GLOBAL buffer indicates that a signal must use a global clock, output enable, register control, or memory enable signal. Global signal availability and usage is device family dependent, refer to device family data sheets for specific details.

If an input pin (or a logic function) feeds directly to the input of GLOBAL, the output of GLOBAL can be used to feed a clock, output enable, register control, or memory enable input to a primitive. A direct connection must exist from the output of GLOBAL to the input of the register or the TRI buffer.

NOTE MAX® 3000 and MAX 7000 devices do not support logic-driven global signals.

Global signals propagate more quickly than array signals and may free up device resources for other logic. GLOBAL should be used to implement global clocking in a portion or all of the project. To verify that registers are globally clocked, you can refer to the Text-Format Report File (.rpt) or HTML-Format Report File (.htm) for the processed project.

As an alternative to using the GLOBAL primitive, when you turn on the Auto Global Clock logic option, the Compiler automatically selects an existing signal in a project to be a global clock, clear, preset, or output enable signal. You can also make a pin or internal logic into a global signal by selecting it and turning on the Global Signal logic option. When you turn on the Ignore GLOBAL Buffers logic option, the Compiler converts all GLOBAL buffers to WIRE primitives.


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