|
|
The EP20K30E, a member of the APEX™ 20KE device family, provides 1,320 registers; 24,576 memory bits; and 30,000 typical gates. It is suitable for memory functions and complex logic functions such as digital signal processing, wide data-path manipulation, data transformation, and microcontrollers. The high-pin-count EP20K30E device contains an embedded array to implement memory functions and a logic array to implement general logic functions. You can integrate entire systems, including 32-bit buses, into a single EP20K30E device. The EP20K30E device meets the low-voltage requirements of 1.8-V applications and supports multiple low-voltage I/O standards.
The EP20K30E is available in 144-pin TQFP packages with 84 I/O pins. (See Note (11)) The device has 1,200 logic elements grouped into 12 MegaLAB™ structures, each of which consists of 10 LABs and one Embedded System Block (ESB). These MegaLAB structures are arranged into six rows and two columns. The embedded array consists of a series of ESBs, each of which provides 2,048 programmable bits that can be configured as product-term logic, look-up-table-based logic, or various types of memory: content-addressable memory (CAM), dual-port RAM, ROM, or FIFO buffers. The EP20K30E JTAG Instruction Register length is 10; the Boundary-Scan Register length is 420; and the JTAG ID code is 080300DD.
Each I/O cell contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. When used as outputs, the I/O registers provide fast clock-to-output times; as inputs, they provide quick setup times. The EP20K30E also contains four dedicated clock pins and four dedicated fast I/O pins for synchronous control signals with large fan-outs. In addition, devices with the suffix, "X," such as EP20K30ETC144-1X devices, include ClockLock® and ClockBoost® phase-locked loop circuitry.
The EP20K30E supports the LVDS I/O standard on dedicated clock signals.
 |
Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EP20K30E device, refer to the current APEX 20K Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site. |
The following table displays the pin-out information for EP20K30E devices:
Function Pad Config. Row Col MegaLAB I/O 144-Pin
No. Pin Column Bank TQFP
Note (10)
I/O 1 DATA6 1 - - 8 105
I/O 3 DATA7 1 - - 8 104
I/O 4 nWS 1 - - 8 103
I/O 5 nRS 1 - - 8 102
I/O 7 nCS 2 - - 8 101
I/O 11 CS 2 - - 8 98
I/O 12 DEV_CLRn 2 - - 8 97
I/O 28 DEV_OE 4 - - 7 84
I/O 34 LOCK2 5 - - 7 80
I/O 35 - 5 - - 7 79
I/O 36 LOCK4 5 - - 7 78
I/O 37 - 5 - - 7 76
I/O 38 - 5 - - 7 75
I/O 47 - - 1 1 6 71
I/O 49 - - 2 1 6 70
I/O 50 - - 3 1 6 69
I/O 52 - - 3 1 6 68
I/O 54 - - 4 1 6 67
I/O 55 - - 5 1 6 66
I/O 58 - - 6 1 6 65
I/O 60 - - 7 1 6 64
I/O 61 - - 7 1 6 63
I/O 62 - - 8 1 6 62
I/O 65 - - 9 1 6 60
I/O 66 - - 10 1 6 59
Function Pad Config. Row Col MegaLAB I/O 144-Pin
No. Pin Column Bank TQFP
Note (10)
I/O 80 - - 10 2 5 50
I/O 82 - - 9 2 5 49
I/O 83 - - 8 2 5 48
I/O 84 - - 8 2 5 47
I/O 86 - - 7 2 5 46
I/O 89 - - 6 2 5 44
I/O 91 - - 5 2 5 43
I/O 92 - - 4 2 5 41
I/O 95 - - 3 2 5 40
I/O 97 - - 2 2 5 39
I/O 98 - - 2 2 5 38
I/O 99 - - 1 2 5 37
I/O 102 - 6 - - 4 35
I/O 103 - 6 - - 4 33
I/O 105 - 6 - - 4 32
I/O 106 - 6 - - 4 31
I/O 107 - 5 - - 4 30
I/O 109 - 5 - - 4 29
I/O 110 - 5 - - 4 27
I/O 112 - 5 - - 4 26
I/O 114 - 4 - - 4 25
I/O 115 - 4 - - 4 24
I/O 125 - 3 - - 3 15
I/O 126 - 3 - - 3 14
I/O 128 - 3 - - 3 13
Function Pad Config. Row Col MegaLAB I/O 144-Pin
No. Pin Column Bank TQFP
Note (10)
I/O 130 - 3 - - 3 11
I/O 131 - 2 - - 3 10
I/O 133 - 2 - - 3 9
I/O 135 - 2 - - 3 8
I/O 137 - 1 - - 3 7
I/O 138 - 1 - - 3 6
I/O 140 - 1 - - 3 3
I/O 141 - 1 - - 3 2
I/O 143 - - 1 2 2 143
I/O 144 - - 2 2 2 142
I/O 145 - - 2 2 2 141
I/O 146 - - 3 2 2 140
I/O 148 - - 3 2 2 139
I/O 149 - - 4 2 2 138
I/O 151 - - 5 2 2 137
I/O 153 - - 6 2 2 136
I/O 154 - - 6 2 2 135
I/O 156 - - 7 2 2 133
I/O 158 - - 8 2 2 132
I/O 161 - - 9 2 2 131
I/O 162 - - 10 2 2 130
I/O 176 - - 10 1 1 122
I/O 177 INIT_DONE - 9 1 1 121
I/O 178 RDYnBSY - 9 1 1 120
I/O 179 CLKUSR - 8 1 1 119
Function Pad Config. Row Col MegaLAB I/O 144-Pin
No. Pin Column Bank TQFP
Note (10)
I/O 180 - - 8 1 1 118
I/O 181 DATA1 - 7 1 1 117
I/O 184 DATA2 - 6 1 1 115
I/O 186 - - 5 1 1 114
I/O 187 - - 5 1 1 113
I/O 188 DATA3 - 4 1 1 112
I/O 192 DATA4 - 3 1 1 111
I/O 194 - - 2 1 1 110
I/O 195 DATA5 - 1 1 1 109
Ded. Fast I/O Pin 69 FAST4 - - - 5 56
Ded. Fast I/O Pin 77 FAST3 - - - 5 53
Ded. Fast I/O Pin 166 FAST1 - - - 1 127
Ded. Fast I/O Pin 173 FAST2 - - - 1 124
INPUT/GCLK 17 CLK4p - - - 8 95
INPUT/GCLK 21 CLK2p - - - 8 92
INPUT/GCLK 117 CLK3p - - - 4 23
INPUT/GCLK 122 CLK1p - - - 4 20
Ded. Config Pin 19 DATA0 - - - 8 94
Ded. Config Pin 20 DCLK - - - 8 93
Ded. Config Pin 22 nCE - - - 8 91
Ded. Config Pin 67 CONF_DONE - - - 5 58
Ded. Config Pin 68 NSTATUS - - - 5 57
Ded. Config Pin 120 NCONFIG - - - 4 22
Ded. Config Pin 123 MSEL1 - - - 4 19
Ded. Config Pin 124 MSEL0 - - - 4 18
Function Pad Config. Row Col MegaLAB I/O 144-Pin
No. Pin Column Bank TQFP
Note (10)
Ded. Config Pin 165 nCEO - - - 1 128
Ded. JTAG Pin 23 TDI - - - 8 90
Ded. JTAG Pin 78 TCK - - - 5 52
Ded. JTAG Pin 79 TMS - - - 5 51
Ded. JTAG Pin 164 TRST - - - 1 129
Ded. JTAG Pin 174 TDO - - - 1 123
PLL Related Pin 15 CLKLK_FB2p - - - 9 96
PLL Related Pin 32 CLKLK_OUT2p - - - 9 81
PLL Related Pin 121 CLKLK_ENA - - - 4 21
VCCIO I/O bank number in parenthesis 5(3)
VCCIO I/O bank number in parenthesis 28(4)
VCCIO I/O bank number in parenthesis 45(5)
VCCIO I/O bank number in parenthesis 61(6)
VCCIO I/O bank number in parenthesis 89(7)
VCCIO I/O bank number in parenthesis 107(8)
VCCIO I/O bank number in parenthesis 116(1)
VCCIO I/O bank number in parenthesis 144(2)
VCCINT 1
VCCINT 16
VCCINT 36
VCCINT 55
VCCINT 73
VCCINT 86
VCCINT 108
VCCINT 125
Function Pad Config. Row Col MegaLAB I/O 144-Pin
No. Pin Column Bank TQFP
Note (10)
VCC_CKLK4 8 - - - - - 100
VCC_CKLK2 27 - - - - - 85
VCC_CKOUT2 29 - - - - 9 83
GNDIO I/O bank number in parenthesis 12(-)
GNDIO I/O bank number in parenthesis 42(-)
GNDIO I/O bank number in parenthesis 72(-)
GNDIO I/O bank number in parenthesis 106(-)
GNDIO I/O bank number in parenthesis 134(-)
GND_CKLK4 9 - - - - - 99
GND_CKLK2 25 - - - - - 88
GND_CKOUT2 30 - - - - 9 82
GND 4
GND 17
GND 34
GND 54
GND 74
GND 77
GND 87
GND 126
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |