Timing Analyzer

Timing Settings Page (Settings Dialog Box)



NOTE You can open this page from the Settings dialog box, or by choosing Timing Settings (Assigments menu).

The pages under this category allow you to specify timing settings that control timing analysis. When timing-driven compilation is engaged, these settings may also affect design fitting. You can use this command to specify project-wide timing requirements, external input or output delays, path-cutting options, and timing analysis reporting restrictions. In addition, you can create clock settings if you want to specify fMAX requirements for selected clock signals in the design.

Pointer Click any item in this picture for information on that item:


timing db Clock Settings tab Other Requirements & Options tab Timing Analysis Reporting Page OK Cancel Files & Directories HDL Input Settings EDA Tool Settings Default Logic Option Settings Default Parameter Settings Compiler Settings Simulator Settings Software Build Settings Stratix GX Registration HardCopy Settings


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