See Also

When creating a design in the Synplify software for use with the Verplex Conformal LEC and the Quartus^® II software, refer the following guidelines:

• For Verilog designs, use all lowercase names on port names, black box entities and source file names. The Quartus II software reduces all names to lowercase when generating the output netlist, and the Conformal LEC software recognizes differences between uppercase and lowercase entity names when performing formal verification.

• The following entities will be treated as black boxes:

  • Library of parameterized modules (LPM) functions and Quartus II megafunctions which do not have a synthesizable model provided.

  • Encrypted intellectual property (IP) cores.

  • Entities that instantiate another black box entity, are parameterized, or do not have a parameterized black box model.

  • Entities that are defined in a design format other than Verilog, VHDL, or EDIF.

• You can instantiate entities that are contained within the following Verilog model files as black boxes:

  Quartus II Black Box Model Files
  File name	Description
  apex20ke_bbox.v	Contains the black box models for APEX™ 20KE designs.
  apexii_bbox.v	Contains the black box models for APEX™ II designs.
  stratix_bbox.v	Contains the black box models for Stratix™ designs.
  stratixgx_bbox.v	Contains the black box models for Stratix™ GX designs.
  cyclone_bbox.v	Contains the black box models for Cyclone™ designs.
  lpms_bbox.v	Contains the black box models LPM functions not in the lpms.v model file.
  mfs_bbox.v	Contains the black box models for megafunctions.
  mfs_hssi_bbox.v	Contains the Stratix GX HSSI black box models.

• The following black box models are provided for the following Altera^® megafunctions and LPM functions:

  Quartus II Black Box Models
  Entity	Entity Names
  lpms_bbox.v	lpm_abs lpm_add_sub lpm_clshift lpm_decode lpm_dff lpm_divide lpm_ff lpm_fifo_dc lpm_fifo lpm_ram_dp lpm_ram_dq lpm_ram_io lpm_rom lpm_shiftreg
  mfs_bbox.v_bbox.v	altcam alt3pram altaccumulate altcdr_rx altcdr_tx altclklock altddio_bidir altddio_in altddio_out altdpram altfp_mult altlvds_rx altlvds_tx altmult_accum altmult_add altpll altqpram altshift_taps altsqrt altsyncram dcfifo hssi_fifo hssi_pll hssi_rx hssi_tx scfifo
  mfs_hssi_bbox	altgxb

The following conditions produce mismatches (either unmapped on non-equivalent points) between the golden (Synplify-generated Verilog Quartus^® Mapping File (.vqm) and revised (Quartus II-generated VQM File) netlists when performing formal verification with the Conformal LEC and Quartus II software:

• The Quartus II software does not preserve port names in user-defined black box entities where the resulting entity is synthesized as a wire in the output netlist, for example, a black box entity that instantiates only a GLOBAL primitive.

• In black box entities where there are an unequal number of inputs and outputs, for example, a black box RAM entity where the width of the data input is greater than the width of the data output, the Quartus II software optimizes the logic in the black box entity and removes the unused RAM bits.

• The Quartus II software may not preserve the hierarchies in black box entities with tri-state buffers, and moves the tri-state buffer to the I/O of the design.

• In designs with combinational feedback loops, the Conformal LEC software may incorrectly insert extra, unmapped cut points in the revised netlist.

• If a port in a black box entity is connected to the default logic value for that port (VCC or GND), the Quartus II software will optimize the logic on the ports for that entity, which results in mismatches in the LEC software. To avoid this, leave the ports unconnected in the golden design to avoid mismatches with the revised design.

• When multiple ports on a black box entity are driven by the same signal, the Quartus II software will push the connections into the entity, and use a single port to drive the internal logic, resulting in the remaining ports being unconnected on the black box entity in the revised netlist.

• Designs with the lpm_dff megafunction may produce mismatches on the entity name and port names due to incorrect capitalization of port names in the revised netlist. You can manually edit the golden netlist to correct the port names.

• For APEX II and Stratix designs contain RAM, optimization of the RAM in the Quartus II software results in creation of new port names. The new port names do not occur in the golden netlist for the design and cause mismatches.

• In designs with the lpm_mult megafunction, and the width of the product is less than the sum of the widths of the inputs, the LEC software may list non-equivalent points, because the Quartus II software truncates the least significant bits in the width of the product.

• In designs with the lpm_mult megafunction when the sum port is not connected, the LEC software may report non-equivalent points on the width of the sum port, due to the Quartus II software, for example, using a default width of 30 for the lpm_width parameter and the LEC software using a default value of one. The model provided for the LEC software uses a default value of one for the sum port, when the port is not connected in the design. This results in a mismatch between the other 29 bits in the port width.

• The Quartus II software packs logic cells that use only registers with logic cells that use only LUTs from the golden design into single logic cells in the revised design, with an instance name taken from the LUT-only logic cell in the golden design. The LEC software attempts to map the register-only logic cell name to an incorrect logic cell in the revised design, resulting in a non-equivalent point. You can manually edit the mapping in the revised design to map to the correct logic cell.

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