Megafunction

altlvds_tx (LVDS) Megafunction

LVDS transmitter megafunction. The altlvds_tx megafunction implements a serialization transmitter. LVDS is one of the high-speed I/O interfaces that uses differential signals without a reference voltage. LVDS uses two wires carrying differential values to create a single channel. These wires are connected to two pins on APEX™ 20KC, APEX 20KE, APEX™ II, ARM®-based Excalibur™, Mercury™, Stratix™, and Stratix™ GX devices to create a single differential LVDS channel. The altlvds_tx megafunction uses ClockLock® PLL circuitry for serialization.

NOTE For Mercury devices, if the altlvds_tx megafunction uses a recovered clock signal that feeds a pin and the DESERIALIZATION_FACTOR parameter setting is 7 or greater, then you must assign the PLL to the center PLL channels on the device. In EP1M120 devices the center channels are channels 4 and 5, and in EP1M350 devices the center channels are channels 9 and 10.

Altera® recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altlvds_tx (tx_in[DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1..0], 
      tx_inclock, sync_inclock, tx_pll_enable, pll_areset)
   WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, REGISTERED_INPUT, MULTI_CLOCK, 
      INCLOCK_PERIOD, OUTCLOCK_DIVIDE_BY, INCLOCK_BOOST, CENTER_ALIGN_MSB, INTENDED_DEVICE_FAMILY,
      OUTPUT_DATA_RATE, INCLOCK_DATA_ALIGNMENT, OUTCLOCK_ALIGNMENT, COMMON_RX_TX_PLL)
   RETURNS (tx_out[NUMBER_OF_CHANNELS-1..0], tx_outclock, tx_coreclock, tx_locked);

 

VHDL Component Declaration:

 
COMPONENT altlvds_tx
   GENERIC (NUMBER_OF_CHANNELS: NATURAL;
      DESERIALIZATION_FACTOR: NATURAL;
      OUTCLOCK_DIVIDE_BY: NATURAL := 0;	  
      REGISTERED_INPUT: STRING := "ON";
      MULTI_CLOCK: STRING := "OFF";
      INCLOCK_PERIOD: NATURAL;
      CLOCK_SETTING: STRING := "UNUSED";
      CENTER_ALIGN_MSB: STRING := "UNUSED";	  
      INTENDED_DEVICE_FAMILY: STRING := "APEX20KE"
      OUTPUT_DATA_RATE: NATURAL := 0;
      OUTCLOCK_ALIGNMENT:  STRING  := "EDGE_ALIGNED";
      INCLOCK_DATA_ALIGNMENT:  STRING := "ON";
      COMMON_RX_TX_PLL:  STRING := "ON");	  	  
   PORT (tx_in: IN STD_LOGIC_VECTOR(DESERIALIZATION_FACTOR*NUMBER_OF_CHANNELS-1 DOWNTO 0);
      tx_inclock: IN STD_LOGIC;
      sync_inclock, pll_areset: IN STD_LOGIC := '0';
      tx_pll_enable: IN STD_LOGIC := '1';	  
      tx_out: OUT STD_LOGIC_VECTOR(NUMBER_OF_CHANNELS-1 DOWNTO 0);
      tx_outclock, tx_coreclock, tx_locked: OUT STD_LOGIC);
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY altera_mf
USE altera_mf.altera_mf_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
tx_in[] Yes Input data. Input port [DESERIALIZATION_FACTOR * NUMBER_OF_CHANNELS-1..0] wide.
tx_inclock Yes LVDS reference input clock.  
sync_inclock No Optional clock for the input registers. If the MULTI_CLOCK parameter is turned on, you must use this port.
tx_pll_enable No Enable control for the LVDS PLL.  
pll_areset No Asynchronously resets all counters to initial values. This port is available for Stratix and Stratix GX devices only.

OUTPUT PORTS

Port Name Required Description Comments
tx_out[] Yes Serialized LVDS data signal. Output port [NUMBER_OF_CHANNELS-1..0] wide. After deserialization, tx_out[n-1] is the first bit transmitted and tx_out[0] is the last bit transmitted for channel one; for channel two, tx_out[2n-1] is the first bit transmitted and tx_out[n] is the last bit transmitted. For more information on bit order, see Application Note 120 (Using LVDS in APEX 20KE Devices).
tx_outclock No External reference clock.  
tx_coreclock No Output clock used to feed non-peripheral logic. This port is available for Mercury, Stratix, and Stratix GX devices only.
tx_locked No Gives the status of the LVDS PLL. When the PLL is locked, this signal is VCC. When the PLL fails to lock, this signal is GND.

 

Parameter Descriptions:
Parameter Type Required Description
NUMBER_OF_CHANNELS Integer Yes Specifies the number of LVDS channels.
DESERIALIZATION_FACTOR Integer Yes Specifies the number of bits per channel. Values are 4, 7, or 8 for APEX 20KE and ARM-based Excalibur devices; 4-10 for APEX II, Stratix, and Stratix GX devices; and 4, 7-12, 14, 16, 18, or 20 for Mercury devices. The value of the INCLOCK_PERIOD parameter is between [125 MHz / DESERIALIZATION_FACTOR] and [1000 MHz / DESERIALIZATION_FACTOR].
REGISTERED_INPUT String No Indicates whether the tx_in[] and tx_outclock ports should be registered. Values are "ON" and "OFF", "TX_CLKIN", and "TX_CORECLK". If omitted the default is "ON". The "TX_CLKIN", and "TX_CORECLK" settings are available for Stratix and Stratix GX devices only.
MULTI_CLOCK String No Indicates whether the sync_inclock port is used for input registering. Values are "ON" and "OFF". If omitted the default is "OFF".
INCLOCK_PERIOD Integer Yes Specifies the period or frequency of the input clock. The default time unit is picoseconds (ps). In AHDL designs only, strings, such as 50.5 MHz, are acceptable.
OUTCLOCK_DIVIDE_BY Integer No Specifies the period of the tx_outclock port as [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY] and the frequency of the tx_outclock port as [INCLOCK_PERIOD / OUTCLOCK_DIVIDE_BY]. The default value for this parameter is the value of the DESERIALIZATION_FACTOR parameter.
INCLOCK_BOOST Integer No The effective clock period used to sample output data. Values are 1, 2, and 4-10. This parameter is available for APEX II and Mercury devices only.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the PLL with the MegaWizard Plug-in Manager (Tools menu) to calculate the value for this parameter.
CENTER_ALIGN_MSB String No Aligns the MSB to the falling edge of the clock instead of the rising edge. This parameter can be used to generate a center aligned clock. Values are "ON", "OFF", and "UNUSED". If omitted, the default is "UNUSED". This parameter is available for APEX II devices only.
OUTPUT_DATA_RATE String Yes Specifies the data rate out of the PLL. The multiplication value for the PLL is INPUT_DATA_RATE / INCLOCK_PERIOD. This parameter is available for Stratix and Stratix GX devices only.
COMMON_RX_TX_PLL String No Specifies whether the Compiler uses the same PLL for both the LVDS receiver and the LVDS transmitter. Values are "ON" and "OFF". If omitted, the default is "ON". This parameter is available for Stratix and Stratix GX devices only.
INCLOCK_DATA_ALIGNMENT String Yes Specifies the alignment of input data with respect to the tx_inclock port. Values are "EDGE_ALIGNED", "CENTER_ALIGNED", "45_DEGREES", "135_DEGREES", "180_DEGREES", "235_DEGREES", "270_DEGREES", and "315_DEGREES". If omitted, the default is "EDGE_ALIGNED". This parameter is available for Stratix and Stratix GX devices only.
OUTCLOCK_ALIGNMENT String Yes Specifies the alignment of output data with respect to the tx_outclock port. Values are "EDGE_ALIGNED", "CENTER_ALIGNED", "45_DEGREES", "135_DEGREES", "180_DEGREES", "235_DEGREES", "270_DEGREES", and "315_DEGREES". If omitted, the default is "EDGE_ALIGNED". This parameter is available for Stratix and Stratix GX devices only.

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