See Also

Parameterized quad-port RAM megafunction. The Quartus^® II software does not provide a paramterized Block Symbol File (.bsf) for the altqpram megafunction, however the MegaWizard^® Plug-In Manager (Tools menu) can create a customized BSF for you. The altqpram megafunction is available for APEX^™ II and Mercury^™ devices only. This megafunction is provided only for backward compatibility in Cyclone^™, Stratix^™, and Stratix^™ GX designs; instead, Altera^® recommends using the altsyncram megafunction.

Altera recommends instantiating this function as described in Using the MegaWizard Plug-In Manager.

This topic contains the following information:

• AHDL Function Prototype (also applies to Verilog HDL)
• VHDL Component Declaration
• VHDL LIBRARY-USE Declaration (not required if the VHDL Component Declaration is used)
• Port Descriptions
• Parameter Descriptions
• Truth Table/Functionality
• Resource Usage

FUNCTION altdpram(wren, data[WIDTH-1..0], wraddress[WIDTHAD-1..0], inclock, inclocken, rden, 
                  rdaddress[WIDTHAD-1..0], outclock, outclocken, aclr)
    WITH (WIDTH, WIDTHAD, NUMWORDS, FILE, INDATA_REG, INDATA_ACLR, WRADDRESS_REG, WRADDRESS_ACLR, 
          WRCONTROL_REG, WRCONTROL_ACLR, RDADDRESS_REG, RDADDRESS_ACLR, RDCONTROL_REG, RDCONTROL_ACLR,
          OUTDATA_REG, OUTDATA_ACLR, USE_EAB)
    RETURNS (q[WIDTH-1..0]);

COMPONENT ALTQPRAM
    GENERIC
      ( OPERATION_MODE            : STRING := "QUAD_PORT";

        WIDTH_WRITE_A             : NATURAL := 1;
        WIDTHAD_WRITE_A           : NATURAL := 1;
        NUMWORDS_WRITE_A          : NATURAL := 2;  -- DEFAULT = 2^WIDTHAD_WRITE_A
        INDATA_REG_A              : STRING := "INCLOCK_A";
        INDATA_ACLR_A             : STRING := "ON";
        WRCONTROL_WRADDRESS_REG_A : STRING := "INCLOCK_A";
        WRCONTROL_ACLR_A          : STRING := "ON";
        WRADDRESS_ACLR_A          : STRING := "ON";

        WIDTH_WRITE_B             : NATURAL := 1;  -- DEFAULT = WIDTH_WRITE_A
        WIDTHAD_WRITE_B           : NATURAL := 1;  -- DEFAULT = WIDTHAD_WRITE_A
        NUMWORDS_WRITE_B          : NATURAL := 2;  -- DEFAULT = 2^WIDTHAD_WRITE_B
        INDATA_REG_B              : STRING := "INCLOCK_B";
        INDATA_ACLR_B             : STRING := "ON";
        WRCONTROL_WRADDRESS_REG_B : STRING := "INCLOCK_B";
        WRCONTROL_ACLR_B          : STRING := "ON";
        WRADDRESS_ACLR_B          : STRING := "ON";

        WIDTH_READ_A              : NATURAL := 1;
        WIDTHAD_READ_A            : NATURAL := 1;
        NUMWORDS_READ_A           : NATURAL := 2;  -- DEFAULT = 2^WIDTHAD_READ_A
        RDCONTROL_REG_A           : STRING := "OUTCLOCK_A";
        RDCONTROL_ACLR_A          : STRING := "ON";
        RDADDRESS_REG_A           : STRING := "OUTCLOCK_A";
        RDADDRESS_ACLR_A          : STRING := "ON";
        OUTDATA_REG_A             : STRING := "UNREGISTERED";
        OUTDATA_ACLR_A            : STRING := "ON";

        WIDTH_READ_B              : NATURAL := 1;  -- DEFAULT = WIDTH_READ_A
        WIDTHAD_READ_B            : NATURAL := 1;  -- DEFAULT = WIDTHAD_READ_A
        NUMWORDS_READ_B           : NATURAL := 2;  -- DEFAULT = 2^WIDTHAD_READ_B
        RDCONTROL_REG_B           : STRING := "OUTCLOCK_B";
        RDCONTROL_ACLR_B          : STRING := "ON";
        RDADDRESS_REG_B           : STRING := "OUTCLOCK_B";
        RDADDRESS_ACLR_B          : STRING := "ON";
        OUTDATA_REG_B             : STRING := "UNREGISTERED";
        OUTDATA_ACLR_B            : STRING := "ON";

        INIT_FILE                 : STRING := "UNUSED";
        MAXIMUM_DEPTH             : NATURAL := 0;  -- DEFAULT = FLOOR(BITS_PER_ESB / MIN _DATA_WIDTH);
     PORT(wren_a, wren_b, inclock_a, inclock_b, 
         outclock_a, outclock_b, inaclr_a, inaclr_b, 
         outaclr_a, outaclr_b	: IN STD_LOGIC := '0';
         data_a       : IN STD_LOGIC_VECTOR(WIDTH_WRITE_A-1 DOWNTO 0) := (OTHERS => '0');
         data_b       : IN STD_LOGIC_VECTOR(WIDTH_WRITE_B-1 WIDTH_READ 0) := (OTHERS => '0');
         wraddress_a  : IN STD_LOGIC_VECTOR(WIDTHAD_WRITE_A-1 WIDTH_READ 0) := (OTHERS => '0');
         wraddress_b  : IN STD_LOGIC_VECTOR(WIDTHAD_WRITE_B-1 WIDTH_READ 0) := (OTHERS => '0');
         inclocken_a, inclocken_b, rden_a, rden_b, 
         outclocken_a, outclocken_b    : IN STD_LOGIC := '1';
         rdaddress_a  : IN STD_LOGIC_VECTOR(WIDTHAD_READ_A-1 WIDTH_READ 0) := (OTHERS => '0');
         rdaddress_b  : IN STD_LOGIC_VECTOR(WIDTHAD_READ_B-1 WIDTH_READ 0) := (OTHERS => '0');
         q_a          : OUT STD_LOGIC_VECTOR(WIDTH_READ_A-1 WIDTH_READ 0);
         q_b          : OUT STD_LOGIC_VECTOR(WIDTH_READ_B-1 WIDTH_READ 0) );
END_COMPONENT;		 

LIBRARY altera_mf
USE altera_mf.altera_mf_components.all;

INPUT PORTS

OUTPUT PORTS

The altqpram function represents asynchronous memory or memory with synchronous inputs and/or outputs.

Synchronous Write to Memory (all inputs registered)
inclock_a/inclock_b inclocken_a/inclocken_b wren_a/wren_b Function   X L L No change. not H H No change. L X No change. H H The memory location pointed to by wraddress_a[]/wraddress_b[] is loaded with data_a[]/data_b[].

Synchronous Read from Memory
inclock_a/inclock_b inclocken_a/inclocken_b rden_a/rden_b Function  X L L No change. not H H No change. L X No change. H H The q_a[]/q_b[] port outputs the contents of the memory location.

Totally asynchronous memory operations occur when neither inclock_a nor outclock_a is connected.

Uses one embedded cell per data output bit.

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