See Also

The Quartus^® II software and VHDL support several library of parameterized modules (LPM) functions and other megafunctions that allow you to implement content-addressable memory (CAM), RAM, and ROM in Quartus II devices. The generic, scalable nature of each of these functions ensures that you can use them to implement any supported type of CAM, RAM, or ROM.

Altera® recommends that you either use Altera-provided megafunctions to implement CAM, RAM, or ROM, or use the MegaWizard® Plug-In Manager (Tools menu) to edit Altera-provided CAM, RAM, or ROM megafunctions. You should not create a megafunction to implement memory or edit the text file for an Altera-provided megafunction. The Quartus II software can also infer RAM from a suitable description in a VHDL Design File (.vhd). See Implementing Inferred RAM for more information.

The following megafunctions can be used to implement CAM, RAM, and ROM in the Quartus II software:

In these logic functions, parameters (or "generics") are used to determine the input and output data widths; the number of data words stored in memory; whether data inputs, address inputs, control inputs, and outputs are registered or unregistered; whether an initial memory content file should be included for a RAM block; and so on. You must declare parameter names and values for an instance of a CAM, RAM, or ROM logic function using a Generic Map Aspect, as described in Using Parameterized Functions & Generics.

You must assign values to all required parameters in the logic function instance; however, you can allow the Quartus II software to use default values for optional parameters, as described in Parameter Value Search Order.

The example below shows a 256 x 8-bit lpm_ram_dq function with separate input and output ports.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY work;
USE work.ram_constants.ALL;

ENTITY ram256x8 IS
   PORT(
      data: IN STD_LOGIC_VECTOR (DATA_WIDTH-1 DOWNTO 0);
      address: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
      we, inclock, outclock: IN STD_LOGIC;
      q: OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 DOWNTO 0));
END ram256x8;

ARCHITECTURE example OF ram256x8 IS

BEGIN
   inst_1: lpm_ram_dq
      GENERIC MAP (lpm_widthad => ADDR_WIDTH,
         lpm_width => DATA_WIDTH)
      PORT MAP (data => data, address => address, we => we,
         inclock => inclock, outclock => outclock, q => q);
END example;

The lpm_ram_dq instance includes a Generic Map Aspect that lists parameter values for the instance. The Generic Map Aspect is based on the Generic Clause in the function's Component Declaration. (The Help topic describing a Quartus II parameterized function shows the Component Declaration for that function.)

For more information, see "Section 9.6: Component Instantiation Statement" in the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual.

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