See Also

The Quartus^® II software can infer RAM from a suitable description in a VHDL Design File (.vhd). This feature can be used to implement RAM in a VHDL design, and is an alternative to implementing a RAM using an Altera-provided megafunction (which is described in Implementing CAM, RAM and ROM). RAM inference is controlled by the Auto RAM Replacement logic option, which is turned on by default.

The Quartus II software recognizes single-port and simple dual-port RAM. True dual-port or quad-port RAM cannot be inferred and must be instantiated using a megafunction. RAM will only be inferred for target families that have appropriate RAM blocks. No RAM will be inferred for devices without RAM blocks. Similarly, if the VHDL Design File describes an asynchronous RAM, no RAM will be inferred when the target family has RAM blocks that do not support an asynchronous mode.

The example below shows ram_infer.vhd, a VHDL Design File that implements a 32 x 32-bit single-clock RAM with separate read and write addresses:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY ram_infer IS
   PORT
   (
      clock: IN   std_logic;
      data:  IN   std_logic_vector (31 DOWNTO 0);
      write_address:  IN   integer RANGE 0 to 31;
      read_address:   IN   integer RANGE 0 to 31;
      we:    IN   std_logic;
      q:     OUT  std_logic_vector (31 DOWNTO 0)
   );
END ram_infer;

ARCHITECTURE rtl OF ram_infer IS

   TYPE mem IS ARRAY(0 TO 31) OF std_logic_vector(31 DOWNTO 0);
   
   SIGNAL ram_block : mem;
   SIGNAL read_address_reg : INTEGER RANGE 0 to 31;
   
BEGIN

   PROCESS (clock)
   BEGIN
      IF (clock'event AND clock = '1') THEN
         IF (we = '1') THEN
            ram_block(write_address) <= data;
         END IF;
         read_address_reg <= read_address;
      END IF;
   END PROCESS;
   
   q <= ram_block(read_address_reg);

END rtl;

The example below shows ram_dual.vhd, a VHDL Design File that implements a 1024 x 4-bit simple dual-port RAM with separate read and write addresses and separate read and write clocks. When the Quartus II software infers a RAM block for a memory with separate read and write clocks, the functionality of the design will change slightly. The behavior when reading and writing to the same address will be different. When the functionality of the design changes, the Quartus II software issues a warning message to alert you and describe the changes.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE ram_package IS

   CONSTANT ram_width : INTEGER := 4;
   CONSTANT ram_depth : INTEGER := 1024;
   
   TYPE word IS ARRAY(0 to ram_width - 1) of std_logic;
   TYPE ram IS ARRAY(0 to ram_depth - 1) of word;
   SUBTYPE address_vector IS INTEGER RANGE 0 to ram_depth - 1;
   
END ram_package;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.ram_package.ALL;

ENTITY ram_dual IS
   PORT
   (
      clock1 : IN   std_logic;
      clock2 : IN   std_logic;
      data   : IN   word;
      write_address: IN  address_vector;
      read_address:  IN  address_vector;
      we     : IN   std_logic;
      q      : OUT  word
   );
END ram_dual;

ARCHITECTURE rtl OF ram_dual IS

   SIGNAL ram_block : RAM;
   SIGNAL read_address_reg : address_vector;
   
BEGIN

   PROCESS (clock1)
   BEGIN
      IF (clock1'event AND clock1 = '1') THEN
         IF (we = '1') THEN
            ram_block(write_address) <= data;
         END IF;
      END IF;
   END PROCESS;

   PROCESS (clock2)
   BEGIN
      IF (clock2'event AND clock2 = '1') THEN
         q <= ram_block(read_address_reg);
         read_address_reg <= read_address;
      END IF;
   END PROCESS;
   
END rtl;

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