See Also

When a design is compiled, the Compiler searches for parameter values for non-VHDL and non-Verilog design files in the following order:

1. As part of the instance of the logic function. For example, in a Text Design File (.tdf), in an instance that is created with an Instance Declaration or an in-line logic function reference, you can declare which parameters are used and optionally assign their values. In a Block Design File (.bdf) or Block Symbol File (.bsf), you can select a symbol and specify parameters and parameter values for that symbol using the Parameters tab of the Symbol Properties dialog box (Edit menu).

2. As part of the instance of the logic function at the next higher hierarchy level. The parameter values for an instance of a logic function apply to the subdesigns of that logic function if the subdesign instances do not have assigned parameter values.

3. In the global project default parameter values specified with the Default Parameter Settings page of the Settings dialog box (Assignments menu). These values are stored in the settings and configuration files for the project.

4. In the optional default value listed in the Parameters Statement(s) of the TDF or the PARAM primitives of the BDF or BSF that defines the logic function. These default values apply only to the file in which they are listed, they are not applied the file's subdesigns.

The Compiler searches for parameter values in VHDL Design Files (.vhd) and Verilog Design Files (.v) in the following order:

1. As part of the instance of the logic function. You can assign parameter values to an instance of a logic function in the Generic Map Aspect of its Component Instantiation Statement for VHDL, and with a Defparam Statement in a Module Instantiation for Verilog HDL.

   or:

   If the VHDL Design File or Verilog Design File is the top-level design file in the project, the Compiler uses the global project default parameter values specified with the Default Parameter Settings page of the Settings dialog box (Assignments menu) as the "instance" parameter values.

2. In the optional default values in the Generic Clause of the VHDL Design File that defines the logic function, or in the default values of the AHDL Include File (.inc) that defines the logic function for Verilog HDL.

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