Megafunctions

altddio_out (DDIO Output) Megafunction

Double Data Rate (DDR) output megafunction. The altddio_out megafunction transmits data on both edges of the reference clock. The altddio_out megafunction is available for APEX™ II, Cyclone™, Mercury™, Stratix™, and Stratix™ GX devices only.

This topic contains the following information:


AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION altddio_out (datain_h[(WIDTH) - (1)..0], datain_l[(WIDTH) - (1)..0], 
      outclock, outclocken, aclr, aset, oe)
   WITH (WIDTH, POWER_UP_HIGH, OE_REG, EXTEND_OE_DISABLE, INTENDED_DEVICE_FAMILY)
   RETURNS (dataout[(WIDTH) - (1)..0]);


VHDL Component Declaration:

 
COMPONENT altddio_out
    GENERIC 
       (WIDTH		    : POSITIVE	:= 1;
        POWER_UP_HIGH	    : STRING  	:= "OFF"
        OE_REG              : STRING  	:= "UNUSED"
        EXTEND_OE_DISABLE   : STRING  	:= "UNUSED");
		
    PORT (data_in_h, data_in_l 	: IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
          outclock 		: IN STD_LOGIC;
          outclocken 		: IN STD_LOGIC := 1; 
          aclr, aset, oe 	: IN STD_LOGIC := 0;
          dataout 		: OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0);
END COMPONENT;


Port Descriptions:

INPUT PORTS

Port Name Required Description Comments
datain_h[] Yes Input data for the falling edge of the outclock port. Input port WIDTH wide.
datain_l[] Yes Input data for the rising edge of the outclock port. Input port WIDTH wide.
outclock Yes Clock signal to register the data output. The dataout port outputs the DDR data on each edge of the outclock clock signal.
outclocken No Clock enable for the outclock port.  
aclr No Asynchronous clear input. The aclr port and the aset port cannot be connected at the same time.
aset No Asynchronous set input. The aclr port and the aset port cannot be connected at the same time.
oe No Output enable for the dataout port.  

OUTPUT PORTS

Port Name Required Description Comments
dataout[] Yes DDR output data port. Output port WIDTH wide. The dataout port should directly feed an output pin in the top-level design.


Parameter Descriptions:
Parameter Type Required Comments
WIDTH Integer Yes Width of the datain_h, datain_l, and dataout ports.
POWER_UP_HIGH String No When both the aset and aclr ports are unused, the POWER_UP_HIGH parameter is available to specify the power-up state of the output ports. Values are "ON" and "OFF". If omitted, the default is "OFF".
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. Create the altddio_out megafunction with the MegaWizard® Plug-in Manager (Tools menu) to calculate the value for this parameter.
OE_REG String No Specifies whether the oe port is registered. Values are "REGISTERED", "UNREGISTERED", and "UNUSED". If omitted, the default is "UNUSED". This parameter is available for APEX II devices only.
EXTEND_OE_DISABLE String No Specifies whether the second oe register should be used. When the second oe register is used, the output pin is held at high impedance for an extra half clock cycle after the oe port goes high. Values are "ON", "OFF", and "UNUSED". If omitted, the default is "UNUSED". This parameter is available for APEX II devices only.


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