See Also

The EP1SGX25, a member of the Stratix^™ GX device family, provides 26,274 registers; 1,944,576 memory bits; and 25,660 logic elements. The dedicated gigabit transceiver block (GXB) circuitry includes up to 16 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES capability at data rates of up to 3.125 gigabits per second (Gbps).  (See Note (12))  It also includes 39 source-synchronous full-duplex channels and provides dedicated circuitry with support for differential I/O standards at up to 1 Gbps when using dynamic phase alignment (DPA), and 840 Mbps when not using DPA. Stratix GX devices also provide enhanced PLLs, fast PLLs, and regional clock networks to increase performance, and provide advanced clock interfacing and clock-frequency synthesis.

Stratix GX devices are suitable for memory functions and complex logic functions, such as digital signal processing, wide data-path manipulation, data transformation, and microcontrollers. The high-pin-count EP1SGX25 device contains a two-dimensional row- and column-based architecture to implement custom logic.

The EP1SGX25 is available in 672-pin FineLine BGA^® packages with 462 I/O pins and 1020-pin FineLine BGA packages with 614 I/O pins.  (See Note (11))  The logic array consists of LABs, with 10 logic elements in each LAB. The device's 25,660 logic elements are grouped into LABs arranged into 46 rows and 62 columns. M512 and M4K memory blocks are grouped into columns across the device and between certain labs, and mega RAMs are located individually or in pairs within the logic array of the device. The M512 and M4K memory blocks contain 576 and 4,608 programmable bits, respectively, and the mega RAMs contains 589,824 RAM bits. The M512 memory block can be configured dual- and single-port RAM, FIFO buffers, and (ROM); the M4K memory block can be configured as true dual-port, dual-port, and single-port RAM, FIFO buffers, and ROM; and the mega RAMs can be configured as true dual-port, dual-port, and single-port RAM, and FIFO buffers.

Each I/O element contains a bidirectional I/O buffer and 6 registers for a complete bidirectional I/O element. The I/O element contains individual input, output, and output enable registers. The input register provides fast setup times, the output register provides fast clock-to-output times, and the output enable register provides fast clock-to-output enable times. The EP1SGX25 also contains 12 dedicated clock pins for control signals with large fan-outs. In addition, all Stratix GX devices include enhanced and fast phase-locked loop (PLL) circuitry. The EP1SGX25 supports ICR and JTAG BST. The EP1SGX25 JTAG Instruction Register length is 10; the Boundary-Scan Register length is 2,157; and the JTAG ID code is 0x020430DD.

Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EP1SGX25 device, refer to the current Stratix GX Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site.

The following table displays the pin-out information for EP1SGX25 devices: