See Also

The EP1S60, a member of the Stratix^™ device family, provides 63,132 registers; 5,215,104 memory bits; and 57,120 logic elements. It includes 116 input and 116 output LVDS channels and provides dedicated circuitry with support for differential I/O standards at up to 840 Mbps. Stratix devices also provide enhanced PLLs, fast PLLs, and regional clock networks to increase performance, and provide advanced clock interfacing and clock-frequency synthesis.

Stratix devices are suitable for memory functions and complex logic functions, such as digital signal processing, wide data-path manipulation, data transformation, and microcontrollers. The high-pin-count EP1S60 device contains a two-dimensional row- and column-based architecture to implement custom logic.

The EP1S60 is available in 956-pin BGA packages with 663 I/O pins, 1020-pin FineLine BGA^® packages with 753 I/O pins, and 1508-pin FineLine BGA packages with 1,002 I/O pins.  (See Note (11))  The logic array consists of LABs, with 10 logic elements in each LAB. The device's 57,120 logic elements grouped into LABs arranged into 73 rows and 90 columns. M512 and M4K memory blocks are grouped into columns across the device and between certain labs, and mega RAMs are located individually or in pairs within the logic array of the device. The M512 and M4K memory blocks contain 576 and 4,608 programmable bits, respectively, and the mega RAMs contains 589,824 RAM bits. The M512 memory block can be configured dual- and single-port RAM, FIFO buffers, and (ROM); the M4K memory block can be configured as true dual-port, dual-port, and single-port RAM, FIFO buffers, and ROM; and the mega RAMs can be configured as true dual-port, dual-port, and single-port RAM, and FIFO buffers.

Each I/O element contains a bidirectional I/O buffer and 6 registers for a complete bidirectional I/O element. The I/O element contains individual input, output, and output enable registers. The input register provides fast setup times, the output register provides fast clock-to-output times, and the output enable register provides fast clock-to-output enable times. The EP1S60 also contains 16 dedicated clock pins for control signals with large fan-outs. In addition, all Stratix devices include enhanced and fast phase-locked loop (PLL) circuitry.

The EP1S60 also supports ICR and JTAG BST. The EP1S60 JTAG Instruction Register length is 10; the Boundary-Scan Register length is 3243; and the JTAG ID code is 0x020060DD.

Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EP1S60 device, refer to the current Stratix Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site.

The following table displays the pin-out information for EP1S60 devices: