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A LogicLock™ region can have a fixed size or an auto size. The Quartus® II software determines the size of auto-size LogicLock regions during compilation. The size is based on the region's contents and is chosen to maximize performance while minimizing routing congestion. If you are satisfied with the size chosen for an auto-size LogicLock region, you can back-annotate this size for use on subsequent compilations.
When you create a LogicLock region by drawing it in the Floorplan Editor, its height and width are set to the dimensions of the region you draw. You can change the region's size by selecting it and using the resizing handles in the middle of each of its edges and in its corners.
When you create a LogicLock region using the LogicLock Regions window, you can use the Size column to set its size to Auto or Fixed. If you select Fixed, you must specify the region's height and width. If you select Auto, the region's size is temporarily set either to the size of the region's parent LogicLock region, or, if the region is a top-level region, to the size of the whole device. If you want to specify a different temporary size, you can select Fixed, set the region to the desired temporary size, and then select Auto.
For APEX™ 20K, APEX™ II, ARM®-based Excalibur™, Cyclone™, Stratix™, and Stratix™ GX devices, the Size tab of the LogicLock Region Properties dialog box allows you to specify width in units of columns, MegaLABs, or LABs/Embedded System Blocks (ESBs), but the Entity Settings File (.esf) always stores LogicLock region width in units of LABs/ESBs. For the purposes of specifying LogicLock region width, an ESB counts as one LAB.
Auto-size LogicLock regions are not supported for Mercury™ devices.
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