See Also

A port is an input or output of a logic function. A port can appear in two locations:

• A port that is an input or output of the current file is declared in the Subdesign Section.

• A port that is an input or output of an instance of a primitive or lower-level design file is used in the Logic Section.

Ports of the Current File

A port that is an input or output of the current file is declared in the following format within the Subdesign Section:

<port name>: <port type> [ = <default port value> ]

The following port types are available:

• INPUT
• OUTPUT
• BIDIR

When a Text Design File (.tdf) is the top-level file in a hierarchy, the port name is synonymous with a pin name. The optional default port value, which is either VCC or GND, can be specified for INPUT and BIDIR port types. This default value is used only if the port is left unconnected when an instance of the TDF is used in a higher-level design file.

In the following example, the input, output, and bidirectional ports of the file are declared in the Subdesign Section:

SUBDESIGN top
(
	foo, bar, clk1, clk2, c[4..0][6..0]	: INPUT = VCC; 
	% VCC is default port value %
	a0, a1, a2, a3, a4			: OUTPUT;
	b[7..0]					: BIDIR;
)

Ports of Instances

A port that is an input or output of an instance of a logic function is connected in the Logic Section. To connect a logic function to other portions of a TDF, you insert an instance of the function with an in-line logic function reference or Instance Declaration or declare a state machine with a State Machine Declaration, and then use ports of the function in the Logic Section.

If you use an in-line logic function reference with positional port association to create an instance of a logic function, the order of the ports, not the names, is important. The order of ports is defined in the Function Prototype for the function.

If you use an Instance Declaration or an in-line logic function reference with named port association to create an instance of a logic function, the names of the ports, not their order, are important.

In the following example, an instance of a D flipflop is declared as the variable reg in the Variable Section, and then used in the Logic Section:

VARIABLE
    reg : DFF;
BEGIN
    reg.clk = clk
    reg.d   = d
    out     = reg.q
END;

Port names are used in the following format in the Logic Section:

<instance name>.<port name>

The <instance name> is a user-defined name for a function. The <port name> is identical to the port name that is declared as an input or output of the file in the Subdesign Section of a lower-level TDF, or to a pin name in another type of design file. This <port name> is synonymous with the pinstub name for the symbol that represents an instance of the design file in a Block Design File (.bdf).

All Altera-provided logic functions have predefined port (pinstub) names, which are shown in the Function Prototype. Commonly used primitive port names are shown in the following table:

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