EDA Tool Settings Section (Settings and Configuration Files)

The EDA Tool Settings section lists all the EDA settings for the tool. For example, it specifies the VHDL library name and the Library Mapping File (.lmf), and how the file should be customized when it is generated for use with a specific simulation or timing analysis tool. The EDA Tool Settings section is located in the Entity Settings File (.esf) and the Project Settings File (.psf). If, however, the EDA Tool Settings section is specified in both the ESF and PSF, the entity level setting in the ESF overrides the PSF setting.

The EDA Tool Settings section keyword is EDA_TOOL_SETTINGS(<name>).

The EDA Tool Settings requires a unique name string, in which you type eda_design_synthesis, eda_simulation, or eda_timing_analysis.

The EDA Tool Settings section contains statements that follow these Usage Code definitions.

The following table shows the EDA Tool Settings section keywords (which are underscore separated), descriptions, legal settings, and usage codes:

Keyword	Settings	Code
`EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE`	On \| Off	A
`EDA_FLATTEN_BUSES`	On \| Off	A
`EDA_GENERATE_POWER_INPUT_FILE`	On \| Off	A
`EDA_GENERATE_SDF_OUTPUT_FILE`	On \| Off	A
`EDA_GENERATE_TIMING_CLOSURE_DATA`	On \| Off	A
`EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION`	On \| Off	A
`EDA_INPUT_DATA_FORMAT`	<data format>	A
`EDA_INPUT_GND_NAME`	<signal name>	A
`EDA_INPUT_VCC_NAME`	<signal name>	A
`EDA_LMF_FILE`	<file name>	A
`EDA_MAINTAIN_DESIGN_HIERARCHY`	On \| Off	A
`EDA_MAP_ILLEGAL_CHARACTERS`	On \| Off	A
`EDA_OUTPUT_DATA_FORMAT`	<netlist page>	A
`EDA_RUN_TOOL_AUTOMATICALLY`	On \| Off	A
`EDA_SHOW_LMF_MAPPING_MESSAGES`	On \| Off	A
`EDA_SIMULATION_RUN_SCRIPT`	<file name>	A
`EDA_TEST_BENCH_DESIGN_INSTANCE_NAME`	<instance name>	A
`EDA_TEST_BENCH_ENABLE_STATUS`	NOT_USED \| TEST_BENCH_MODE \| COMMAND_MACRO_MODE	A
`EDA_TEST_BENCH_ENTITY_MODULE_NAME`	<module name>	A
`EDA_TEST_BENCH_FILE_NAME`	<file name>	A
`EDA_TEST_BENCH_RUN_FOR`	<time unit>	A
`EDA_TIME_SCALE`	<time delay unit>	A
`EDA_TRUNCATE_LONG_HIERARCHY_PATHS`	On \| Off	A
`EDA_USE_IBIS_RLC_TYPE`	Minimum \| Typical \| Maximum	A
`EDA_VHDL_LIBRARY`	<name>	B
`EDA_WRITE_DEVICE_CONTROL_PORTS`	On \| Off	A
`RESYNTHESIS_EXTRA_DEBUGGING_INFORMATION`	On \| Off (Default=Off)	A
`RESYNTHESIS_OPTIMIZATION_EFFORT`	Normal \| Low (Default=Normal)	A
`RESYNTHESIS_PHYSICAL_SYNTHESIS`	Normal \| Advanced (Default=Normal)	A
`RESYNTHESIS_RETIMING`	Full \| Off \| Core (Default=Full)	A
`USE_GENERATED_PHYSICAL_CONSTRAINTS`	On \| Off (Default=On)	A

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