Settings and Configuration Files

EDA_MAP_ILLEGAL_CHARACTERS



Maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus® II hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files (.vo). Turning on this option also maps other illegal non-alphanumeric characters, including brackets [], parentheses, (), angle brackets <>, and braces {} to underscore (_).

- PLDWorld -

 

Created by chm2web html help conversion utility.