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The Compiler Settings section lists the Compiler settings for the entity that has the compilation focus. The Compiler Settings section is located in the Compiler Settings File (.csf).
The Compiler Settings section keyword is COMPILER_SETTINGS.
The Compiler Settings section contains statements that follow these Usage Code definitions.
The following table shows the Compiler Settings section keywords (which are underscore separated), descriptions, legal settings, and usage codes:
| Keyword | Settings | Code |
|---|---|---|
ADV_NETLIST_OPT_FIT_LE_DUPLICATION |
On | Off (Default=Off) | A |
ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTH |
On | Off (Default=Off) | A |
ADV_NETLIST_OPT_RETIME_CORE_AND_IO |
On | Off (Default=On) | A |
ADV_NETLIST_OPT_SYNTH_GATE_RETIME |
On | Off (Default=Off) | A |
ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO |
On | Off (Default=Off) | A |
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP |
On | Off (Default=Off) | A |
DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 |
MegaLAB™ column 1 | MegaLAB column 2 (Default=MegaLAB column 1) | A |
DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 1) | A |
DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 |
Lower to 1ESB Upper to 1 | Lower to 1 Upper to 2 | Lower to 2 Upper to 1 (Default=Lower to 1ESB Upper to 1) | A |
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 1) | A |
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 1) | A |
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 1) | A |
DPRAM_DEEP_MODE_INPUT_EPXA4_10 |
MegaLAB column 3 | MegaLAB column 4 (Default=MegaLAB column 3) | A |
DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 |
MegaLAB column 3 | MegaLAB column 4 (Default=MegaLAB column 3) | A |
DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 |
MegaLAB column 3 | MegaLAB column 3ESB | MegaLAB column 4 | MegaLAB column 4ESB (Default=MegaLAB column 3) | A |
DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 |
DPRAM0 to 2 DPRAM1 to 2ESB | DPRAM0 to 1 DPRAM1 to 2 (Default=DPRAM0 to 1 DPRAM1 to 2) | A |
DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 |
DPRAM0 to 3 DPRAM1 to 4 | A |
DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 |
DPRAM0 to 1 DPRAM1 to 2 | A |
DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 |
DPRAM0 to 3 DPRAM1 to 4 | A |
DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 |
DPRAM0 to 1ESB DPRAM1 to 1 | DPRAM0 to 1 DPRAM1 to 2 | DPRAM0 to 2 DPRAM1 to 1 (Default=DPRAM0 to 1 DPRAM1 to 2) | A |
DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 |
DPRAM0 to 3 DPRAM1 to 4ESB | DPRAM0 to 3ESB DPRAM1 to 4 | DPRAM0 to 3 DPRAM1 to 3ESB | DPRAM0 to 4ESB DPRAM1 to 4 | DPRAM0 to 4ESB DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 3ESB | DPRAM0 to 3ESB DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 4ESB (Default=DPRAM0 to 3 DPRAM1 to 4ESB) | A |
DPRAM_INPUT_EPXA4_10 |
Default input routing options | DPRAM0 to 3 DPRAM1 to 4 | DPRAM0 to 4 DPRAM1 to 3 | DPRAM0 to 3 DPRAM1 to 3ESB | DPRAM0 to 4 DPRAM1 to 4ESB (Default=Default input routing options) | A |
DPRAM_OTHER_SIGNALS_EPXA4_10 |
Default other routing options | DPRAM0 to 3 DPRAM1 to 4 | DPRAM0 to 4 DPRAM1 to 3 (Default=Default other routing options) | A |
DPRAM_OUTPUT_EPXA4_10 |
Default output routing options | DPRAM0 to 3 DPRAM1 to 4ESB | DPRAM0 to 3ESB DPRAM1 to 4 | DPRAM0 to 3 DPRAM1 to 3ESB | DPRAM0 to 4ESB DPRAM1 to 4 | DPRAM0 to 4ESB DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 3ESB | DPRAM0 to 3ESB DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 4ESB (Default=Default output routing options) | A |
DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 |
DPRAM0 to 3 DPRAM1 to 4 | DPRAM0 to 3 DPRAM1 to 3ESB | DPRAM0 to 4 DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 4ESB (Default=DPRAM0 to 3 DPRAM1 to 4) | A |
DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 |
DPRAM0 to 3 DPRAM1 to 4 | DPRAM0 to 4 DPRAM1 to 3 (Default=DPRAM0 to 3 DPRAM1 to 4) | A |
DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 |
DPRAM0 to 3 DPRAM1 to 4ESB | DPRAM0 to 3ESB DPRAM1 to 4 | DPRAM0 to 3 DPRAM1 to 3ESB | DPRAM0 to 4ESB DPRAM1 to 4 | DPRAM0 to 4ESB DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 3ESB | DPRAM0 to 3ESB DPRAM1 to 3 | DPRAM0 to 4 DPRAM1 to 4ESB (Default=DPRAM0 to 3 DPRAM1 to 4ESB) | A |
DPRAM_WIDE_MODE_INPUT_EPXA4_10 |
Lower to 3 Upper to 4 | Lower to 3 Upper to 3ESB | Lower to 4 Upper to 3 | Lower to 4 Upper to 4ESB (Default=Lower to 3 Upper to 4) | A |
DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 |
MegaLAB column 3 | MegaLAB column 4 (Default=MegaLAB column 3) | A |
DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 |
Lower to 3 Upper to 4ESB | Lower to 3ESB Upper to 4 | Lower to 3 Upper to 3ESB | Lower to 4ESB Upper to 4 | Lower to 4ESB Upper to 3 | Lower to 4 Upper to 3ESB | Lower to 3ESB Upper to 3 | Lower to 4 Upper to 4ESB (Default=Lower to 3 Upper to 4ESB) | A |
DRC_FANOUT_EXCEEDING |
On | Off (Default=On) | A |
DRC_REPORT_FANOUT_EXCEEDING |
On | Off (Default=Off) | A |
DRC_REPORT_TOP_FANOUT |
On | Off (Default=Off) | A |
DRC_TOP_FANOUT |
<integer> (Default=50) | A |
ENABLE_SYNCH_INPUT_REGISTER_1S25 |
On | Off | A |
EXCALIBUR_HEX_FILE |
<file name> | A |
FAMILY |
<device family> (Default=APEX™20KE) | A |
FAST_FIT_COMPILATION |
On | Off (Default=Off) | A |
FIT_ONLY_ONE_ATTEMPT |
On | Off | A |
FLEX®10K_MAX_PERIPHERAL_OE
|
<integer> | A |
FINAL_PLACEMENT_OPTIMIZATION |
Always | Never | Automatically (Default=Automatically) | A |
FOCUS_ENTITY_NAME |
<path> | A |
INC_PLC_MODE |
On | Off | A |
INITIAL_PLACEMENT_CONFIGURATION |
<integer> (Default=1) | A |
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT |
On | Off (Default=Off) | A |
LOGICLOCK_INCREMENTAL_COMPILE_FILE |
<file name> | A |
MERGE_HEX_FILE |
On | Off (Default=Off) | A |
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING |
On | Off (Default=On) | A |
OPTIMIZE_TIMING |
Off | Normal compilation | Extra effort (Default=Normal compilation) | A |
PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 2) | A |
PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 2) | A |
ROUTING_BACK_ANNOTATION_MODE |
Off | Normal | Advanced | A |
RUN_DRC_DURING_COMPILATION |
On | Off (Default=Off) | A |
RUN_FITTER_IN_SIGNALPROBE_MODE |
On | Off (Default=Off) | A |
SAVE_DISK_SPACE |
On | Off (Default=On) | A |
SIGNALPROBE_ALLOW_OVERUSE |
On | Off (Default=Off) | A |
SIGNALPROBE_AUTO_ASSIGN |
<integer> (Default=0) | A |
SIGNALPROBE_COMPILATION |
On | Off (Default=On) | A |
SIGNALPROBE_ROUTING |
ALL_SIGNAL_PROBE | NEW_SIGNAL_PROBE (Default=ALL_SIGNAL_PROBE) | A |
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES |
On | Off (Default=Off) | A |
SPEED_DISK_USAGE_TRADEOFF |
Normal | Smart (Default=Normal) | A |
STRIPE_TO_PLD_BRIDGE_EPXA4_10 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 1) | A |
STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 |
MegaLAB column 1 | MegaLAB column 2 (Default=MegaLAB column 2) | A |
TAN_SCRIPT_FILE |
<file name> | A |
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