See Also

Specifies where the embedded processor core debug extensions are routed on the device. In EPXA10 devices, the three MSB bits of the trace port debug inputs from the programmable logic device (PLD) are always routed to the same MegaLAB^™ column as the PLD-To-Stripe Bridge. In EPXA4 devices, the three LSB bits of the trace port debug inputs from the PLD, the debug request signal, and two debug inputs from the PLD are always routed to the same MegaLAB column as the Stripe-To-PLD Bridge.