Inhalt

1. Finite State Machines and VHDL

1.1 FSM Types

1.1.1 Medvedev Machine

1.1.2 Medvedev Example

1.1.3 Waveform Medvedev Example

1.1.4 Moore Machine

1.1.5 Moore Example

1.1.6 Waveform Moore Example

1.1.7 Mealy Machine

1.1.8 Mealy Example

1.1.9 Waveform Mealy Example

1.2 Modelling Aspects

1.2.1 Registered Output

1.2.2 How many Processes?

1.2.3 Safe FSMs

1.3 FSM and Simulation

1.3.1 Clocked Process Simulation (1)

1.3.2 Clocked Process Simulation (2)

1.3.3 Clocked Process Simulation (3)

1.3.4 Recommodations for Simulation

1.4 FSM and Synthesis

1.4.1 FlipFlop and Latch Attributes

1.4.2 State Processes and Synthesis