1.1.5 Moore Example

architecture RTL of MOORE_TEST is
    signal STATE,NEXTSTATE : STATE_TYPE ;
begin
    REG: process (CLK, RESET) begin
       if RESET=`1` then   STATE <= START ;
       elsif CLK`event and CLK=`1` then
           STATE <= NEXTSTATE ;
       end if ;    end process REG ;
    CMB: process (A,B,STATE) begin
       NEXTSTATE <= STATE ;
       case STATE is
          when START  => if (A or B)=`0` then
                            NEXTSTATE <= MIDDLE ;
                         end if ;
          when MIDDLE => if (A and B)=`1` then
                            NEXTSTATE <= STOP ;
                         end if ;
          when STOP   => if (A xor B)=`1` then
                            NEXTSTATE <= START ;
                         end if ;
          when others => NEXTSTATE <= START ;
          end case ;     end process CMB ;
    -- concurrent signal assignments for output
    Y <= ,1` when STATE=MIDDLE else ,0` ;
    Z <= ,1` when STATE=MIDDLE
               or STATE=STOP else ,0` ;
end RTL ;