1.3.4 Recommodations for Simulation

Don`t assign stimulis together with clock edge
Use two state processes
Use concurrent signal assignments for clock generation
(=> will be updated in prior Δ -Cycles than processes)

CLK <= not CLK after PERIOD/2 ;

process begin
    CLK <= not CLK ;
    wait for PERIOD/2 ;
end process ;

Δ_m,n => CLK in update list for Δ_m+i,1

Δ_m+i, ₁ => CLK update

Δ_m,n => CLK update (because of wait ...)

Δ_m+i, ₁ => Update of signals in update list

=> Process execution

Δ_m+i, ₂ => CLK update