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You can create a user-defined megafunction or macrofunction in Verilog HDL by generating an AHDL Include File (.inc), which contains an AHDL Function Prototype, for each lower-level logic function that is instantiated in the top-level Verilog Design File (.v). You can either manually create the AHDL Include File, or create an AHDL Include File from any Quartus^®-supported design file in the Quartus^® II Text Editor, Block Editor, or Symbol Editor. In addition, the Quartus II MegaWizard^® Plug-In Manager automatically generates an AHDL Include File containing a Function Prototype when you use it to create a custom megafunction variation. The AHDL Include File must have the same filename as the design file, with the extension .inc.

After you create the user-defined function, you can then instantiate the function in a Verilog Design File as described in Using a Quartus II Logic Function.

To use a particular logic function in multiple projects, use the User Libraries page of the Settings dialog box (Assignments menu) to specify the directory that contains the function's design file and AHDL Include File as a user library for each project. Make sure you use the User Libraries page for each project. You can also save copies of the files to the directory of an existing user library. Otherwise, you must save copies of the files to the directory containing the project that will use the custom function. For information on using parameterized macrofunctions and megafunctions (such as library of parameterized modules [LPM] functions), go to Using Parameterized Functions.

The example below shows reg12.v, a Verilog Design File for a 12-bit register design. After you create an AHDL Include File, reg12.v can be instantiated in a Verilog Design File that is higher in the project hierarchy. Note that the reg variable used in the Register Inference is listed with the reg keyword (it is defined as a reg data type) in the Module Item Declaration at the beginning of the Module Declaration.

module reg12 (d, clk, q);

   input   [11:0] d; 
   input   clk;
   output  [11:0] q;

   reg     [11:0] q;

   always @ (posedge clk)
      q = d;
     
endmodule

The example below shows reg24.v, a Verilog Design File that declares reg24, then instantiates the reg12 function without requiring any Module Declaration. During design processing, the Compiler automatically refers to reg12.inc for information on port names and their order.

module reg24 (d, clk, q);

   input   [23:0] d; 
   input   clk;
   output  [23:0] q;

   reg12 reg12a (.q (q[11:0]), .d (d[11:0]), .clk (clk));
   reg12 reg12b (.q (q[23:12]), .d (d[23:12]), .clk (clk));
     
endmodule

When instantiating user-defined functions, you must explicitly create an AHDL Include File that contains a Function Prototype specifying all of the ports of the function. In contrast, AHDL Include Files for Altera-provided megafunctions are installed automatically in the \quartus\libraries\megafunctions directory.

For more information, see "Section 12.1.2: Module Instantiation" in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

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