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In Verilog HDL, you can use a Module Instantiation to create an instance of a parameterized function (including a library of parameterized modules [LPM] function) supported by the Quartus^® II software.

You can instantiate parameterized functions with a Module Instantiation in the same way as unparameterized functions, as described in Using a Quartus II Logic Function and Implementing a User-Defined Megafunction and Macrofunction, with a few additional steps:

• The logic function instance must include a Defparam Statement for each logic function parameter to which you want to assign a value. A Defparam Statement can assign a value to any parameter defined in the WITH clause of the logic function's AHDL Function Prototype. (The help topic describing a Quartus II parameterized function shows the Function Prototype for that function. The Function Prototype for a user-defined parameterized function is in the AHDL Include File (.inc) for the function.) You must have a Defparam Statement for each required parameter in the logic function instance; however, you can allow the Quartus II software to use default values for optional parameters, as described in Parameter Value Search Order.

  The syntax for a Quartus^®-supported Defparam Statement is as follows:

  defparam <instance name>.<parameter name>=<parameter value>

  The parameter value can be an integer, arithmetic expression, text string, or another parameter that is declared in the same module as the Defparam Statement.

  You can also use Module Instantiations with Defparam Statements to create instances of Verilog HDL modules. For Verilog HDL modules, a Defparam Statement assigns a value to a parameter that is defined in the parameter declaration in the Module Declaration of the module. You can either assign values to the parameters or use their default values. For more information, go to "12.2: Overriding Module Parameter Values" in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

• A Defparam Statement can pass parameters only to a design file that is one level lower than the current design file. For example, if the file top.v instantiates middle.v, which instantiates bottom.v, top.v can pass parameter values to middle.v, but not to bottom.v. You must explicitly pass parameters from middle.v to bottom.v.

• Because parameterized functions do not necessarily have default values for unconnected inputs, you must ensure that all required ports are connected.

The following example shows reg24lpm.v, a Verilog Design File (.v) for a 24-bit register that includes Module Instantiations for reg12a and reg12b, two instances of the Altera-provided lpm_ff parameterized megafunction. The Defparam Statement for each instance of lpm_ff defines the register width as 12 bits by setting the lpm_width parameter value to 12.

module reg24lpm (d, clk, q);

    input   [23:0] d; 
    input   clk;
    output  [23:0] q;

    lpm_ff reg12a (.q (q[11:0]), .data (d[11:0]), .clock (clk));
        defparam reg12a.lpm_width = 12;

    lpm_ff reg12b (.q (q[23:12]), .data (d[23:12]), .clock (clk));
        defparam reg12b.lpm_width = 12;
     
endmodule

For more information, see "Section 12.1.2: Module Instantiation" in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

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