See Also

In Verilog HDL, you can use a Module Instantiation to insert an instance of a Quartus^® II logic function—a primitive or megafunction—into a Verilog Design File (.v). When it processes the Module Instantiation, the Compiler refers to the AHDL Include File (.inc) for the logic function, and automatically connects logic function ports listed in the INC File's Function Prototype to the signals or interface port of the instantiated module. INC Files containing Function Prototypes for Quartus II megafunctions are provided in the \quartus\libraries\megafunctions directory. Function Prototypes for Quartus II primitives are built into the Quartus II software, and are documented in Quartus II Help.

Verilog HDL does not directly support logic functions or ports with names that are Verilog HDL keywords or that begin with a number. To use these functions, you must prefix the name with \. For example, to use a user-defined function called 1example, you must specify \1example in your Module Instantiation. The Quartus II software automatically removes the \ prefix of any logic function or port name during processing. The \ prefix is also omitted from the Report window, HTML-Format Report File (.htm), and Text-Format Report File (.rpt) generated during compilation. Additional requirements for using parameterized functions (such as library of parameterized modules [LPM] functions), are described in Using Parameterized Functions.

In the example below, a Module Instantiation creates an instance of a DFF primitive and a TRI primitive.

module compinst (data, clock, clearn, presetn, a, b, q_out,
                 t_out);

    input   data, clock, clearn, presetn, a, b; 
    output  q_out, t_out;

    dff dff1 (.d (data), .q (q_out), .clk (clock), .clrn 
    (clearn), .prn (presetn));
    
    tri tri1 (b, a, t_out);

endmodule

A Module Instantiation is used to create a single instance of the DFF primitive. The ports in the list of module connections of the dff1 primitive instance are connected by name to the Function Prototype of the DFF primitive; ports are mapped directly to signals, regardless of the order in which they are listed. The d port of the DFF primitive is mapped to data, q to q_out, clk to clock, clrn to clearn, and prn to presetn.

A Module Instantiation is also used to create a single instance of the TRI primitive. The ports in the tri1 primitive instance are associated by position: the first port (in) in the TRI primitive is mapped to b, the second port (oe) to a, and the third port (out) to t_out.

The Help topic describing an Altera-provided function shows the Function Prototype for that function.

For more information, see "Section 12.1.2: Module Instantiation" in the IEEE Std 1364-1995 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.

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