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To create a default AHDL Include File (.inc) that represents the entities in the current Text Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), Block Design File (.bdf), or Block Symbol File (.bsf):

1. If you have not already done so, create a new project or open an existing project.

2. If you have not already done so, create or open the design file for which you want to create a default AHDL Include File.

3. If necessary, if you are creating an AHDL Include File for an EDIF Input File, specify EDIF conversion information.

4. Choose Create/Update > Create AHDL Include Files for Current File (File menu).  More Details

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