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Displays information regarding usage of LVDS receiver PLLs and LVDS transmitter PLLs. This section is omitted if the design does not include LVDS PLLs or if you specify an ACEX® 1K, FLEX® 6000, Cyclone™, FLEX 10KE, MAX® 3000, MAX 7000, Stratix™, or Stratix™ GX device for compilation.
Information is provided as follows:
| Heading | Description | Value |
|---|---|---|
| Name | Shows the LVDS instance name. | <LVDS instance name> |
| Function | Shows how the LVDS interface is functioning. | Transmitter | Receiver |
| Clock0 | Shows the Clock0 instance name. | <Clock0 instance name> |
| Clock1 | Shows the Clock1 instance name. | <Clock1 instance name> |
| Data Width | Shows the value you set for the DESERIALIZATION_FACTOR
parameter for the LVDS receiver
or transmitter megafunction.
This parameter specifies the number of bits per channel. |
4 | 7 | 8 |
The following example shows the LVDS section for a sample design:
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- PLDWorld - |
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