Support for Verilog instances

The FLI functions are designed to work with VHDL designs and VHDL objects. However, the functions for traversing the design hierarchy also recognize Verilog instances.

The following functions operate on Verilog instances as indicated:

mti_GetTopRegion()

Gets the first top-level module. Use mti_NextRegion( ) to get additional top-level modules.

mti_GetPrimaryName()

Gets the module name.

mti_GetSecondaryName()

Returns NULL for Verilog modules.

The following functions operate on Verilog instances in the same manner as they operate on VHDL instances.

mti_CreateRegion()	mti_GetRegionFullName()
mti_FindRegion()	mti_GetRegionName()
mti_FirstLowerRegion()	mti_GetRegionSourceName()
mti_GetCurrentRegion()	mti_HigherRegion()
mti_GetLibraryName()	mti_NextRegion()

All other FLI functions operate only on VHDL instances and objects. Specifically, the functions that operate on VHDL signals and drivers cannot be used on Verilog nets and drivers. For example, a call to mti_FirstSignal( ) on a Verilog region always returns NULL. You must use the PLI or VPI functions to operate on Verilog objects.

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