mti_FindRegion()

Finds a region by name.

Syntax

region_id = mti_FindRegion( name ) 

Returns

Name	Type	Description
region_id	mtiRegionIdT	A handle to the region or NULL if the region is not found

Arguments

Name	Type	Description
name	char *	The name of the region to be found

Description

mti_FindRegion() returns a handle to the specified region. The region name can be either a full hierarchical name or a relative name. A relative name is relative to the current region set by the simulator's environment command. The default current region is the foreign architecture region during elaboration and the top-level region after elaboration is complete.

mti_FindRegion() can be used to obtain a handle to either a VHDL region or a Verilog region.

During elaboration, design units that have not yet been instantiated will not be found by mti_FindRegion().

Related functions

mti_FirstLowerRegion()

mti_GetCallingRegion()

mti_GetCurrentRegion()

mti_GetTopRegion()

mti_HigherRegion()

mti_NextRegion()

Example

FLI code

#include <mti.h>

void loadDoneCB( void * param )
{
  char *       region_name;
  mtiRegionIdT regid;

  mti_PrintMessage( "\nLoad Done phase:\n" );

  regid = mti_FindRegion( "top" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  regid = mti_FindRegion( "inst1" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  /* The i1 region is not found here because it is not a subregion
  * of /top, which is the current context.
  */
  regid = mti_FindRegion( "i1" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  regid = mti_FindRegion( "inst1/flip" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  regid = mti_FindRegion( "/top/inst1/toggle" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  char *       region_name;
  mtiRegionIdT regid;

  mti_AddLoadDoneCB( loadDoneCB, 0 );

  mti_PrintMessage( "\nElaboration phase:\n" );

  regid = mti_FindRegion( "top" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  regid = mti_FindRegion( "inst1" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  regid = mti_FindRegion( "i1" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

  regid = mti_FindRegion( "flip" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }

 /* The toggle instance is not found here because it has not
  * yet been instantiated.
  */
  regid = mti_FindRegion( "/top/inst1/toggle" );
  if ( regid ) {
    region_name = mti_GetRegionFullName( regid );
    mti_PrintFormatted( "Found region %s\n", region_name );
    mti_VsimFree( region_name );
  }
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity inv is
  generic ( delay : time := 5 ns );
  port ( a : in bit;
         b : out bit
       );
end inv;

architecture b of inv is
begin
  b <= a after delay;
end b;

entity mid is
end mid;

architecture a of mid is

  signal s1 : bit := '0';
  signal s2 : bit := '0';
  signal s3 : bit := '0';
  signal s4 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

  component inv is
    generic ( delay : time := 5 ns );
    port ( a : in bit;
           b : out bit
         );
  end component;

begin

  flip : inv port map ( s3, s4 );

  i1 : for_model;

  s1 <= not s1 after 5 ns;
  s3 <= not s3 after 5 ns;

  toggle : inv port map ( s1, s2 );

end a;

entity top is
end top;

architecture a of top is
  component mid is
  end component;
begin
  inst1 : mid;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.mid(a)
# Loading work.inv(b)
# Loading work.for_model(a)
# Loading ./for_model.sl
# 
# Elaboration phase:
# Found region /top
# Found region /top/inst1
# Found region /top/inst1/i1
# Found region /top/inst1/flip
# 
# Load Done phase:
# Found region /top
# Found region /top/inst1
# Found region /top/inst1/flip
# Found region /top/inst1/toggle
VSIM 1> run 10
VSIM 2> quit 

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