mti_FindProjectEntry()

Gets the value of an entry in the project (.ini) file.

Syntax

value = mti_FindProjectEntry( section, name, expand ) 

Returns

Name	Type	Description
value	char *	The value of the specified entry or NULL if the entry is not found

Arguments

Name	Type	Description
section	char *	The name of the section in the project file in which the entry resides
name	char *	The name of the entry
int	expand	If this parameter is non-zero, then environment variables in the entry are expanded; otherwise they are not

Description

mti_FindProjectEntry() returns the value of the specified entry from the specified section of the project file (modelsim.ini). Expansion of environment variables in the entry's value is controlled by the expand parameter. The comparison against the section and name strings is not case-sensitive.

The caller is responsible for freeing the returned pointer with mti_VsimFree().

Related functions

mti_WriteProjectEntry()

Example

FLI code

#include <mti.h>

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  char * entry;

  entry = mti_FindProjectEntry( "myconfig", "myentry", 0 );
  mti_PrintFormatted( "[myconfig] myentry = %s\n", entry );
  mti_VsimFree( entry );

  entry = mti_FindProjectEntry( "myconfig", "myentry", 1 );
  mti_PrintFormatted( "[myconfig] myentry = %s\n", entry );
  mti_VsimFree( entry );

  entry = mti_FindProjectEntry( "library", "std", 0 );
  mti_PrintFormatted( "[Library] std = %s\n", entry );
  mti_VsimFree( entry );

  entry = mti_FindProjectEntry( "VSIM", "resolution", 1 );
  mti_PrintFormatted( "[vsim] Resolution = %s\n", entry );
  mti_VsimFree( entry );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity top is
end top;

architecture a of top is

  signal s1 : bit := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin

  i1 : for_model;

  s1 <= not s1 after 5 ns;

end a; 

Project file

[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys

work = work

[myconfig]
myentry = $MODEL_TECH/xyz

[vcom]
; Turn on VHDL-1993 as the default. Normally is off (VHDL-1987).
; VHDL93 = 1

; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; .ini file has Explict enable so that std_logic_signed/unsigned
; will match synthesis tools behavior.
Explicit = 1

[vlog]

; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1

; Turns on incremental compilation of modules 
; Incremental = 1

[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ns

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
UserTimeUnit = default

; Default run length
RunLength = 100

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Stop the simulator after an assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic

; VSIM Startup command
; Startup = do startup.do

; File for saving command transcript
TranscriptFile = transcript

; Specify whether paths in simulator commands should be described 
; in VHDL or Verilog format. For VHDL, PathSeparator = /
; for Verilog, PathSeparator = .
PathSeparator = /

; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :

; Control VHDL files opened for write
;   0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0

; Control number of VHDL files open concurrently
;   This number should always be less then the 
;   current ulimit setting for max file descriptors
;   0 = unlimited
ConcurrentFileLimit = 40 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
# [myconfig] myentry = $MODEL_TECH/xyz
# [myconfig] myentry = .../modeltech/sunos5/xyz
# [Library] std = $MODEL_TECH/../std
# [vsim] Resolution = ns
VSIM 1> run 5
VSIM 2> quit 

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