mti_FindPort()

Finds a port signal in a port interface list.

Syntax

signal_id = mti_FindPort( list, name ) 

Returns

Name	Type	Description
signal_id	mtiSignalIdT	A handle to a VHDL port signal or NULL if the signal is not found

Arguments

Name	Type	Description
list	mtiInterfaceListT *	A pointer to a list of interface items
name	char *	The name of the signal to be found in the list

Description

mti_FindPort() searches linearly through the specified interface list and returns a handle to the port signal whose name matches the specified name. The search is not case-sensitive.

Related functions

mti_FindSignal()

Example

FLI code

#include <mti.h>

typedef struct {
  mtiProcessIdT procid;
  mtiSignalIdT  bitsig;
  mtiSignalIdT  intsig;
  mtiSignalIdT  realsig;
} instanceInfoT;

void checkValues( void * param )
{
  double          real_val;
  instanceInfoT * inst = (instanceInfoT*)param;

  mti_PrintFormatted( "Time [%d,%d] delta %d:\n",
                     mti_NowUpper(), mti_Now(), mti_Delta() );
  mti_PrintFormatted( "  %s = %d\n",
                     mti_GetSignalName( inst->bitsig ),
                     mti_GetSignalValue( inst->bitsig ) );
  mti_PrintFormatted( "  %s = %d\n",
                     mti_GetSignalName( inst->intsig ),
                     mti_GetSignalValue( inst->intsig ) );
  (void) mti_GetSignalValueIndirect( inst->realsig, &real_val );
  mti_PrintFormatted( "  %s = %g\n",
                     mti_GetSignalName( inst->realsig ), real_val );
  mti_ScheduleWakeup( inst->procid, 5 );
}

void cleanupCallback( void * param )
{
  mti_PrintMessage( "Cleaning up...\n" );
  free( param );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  instanceInfoT * inst;

  inst          = (instanceInfoT *)malloc( sizeof(instanceInfoT) );
  inst->intsig  = mti_FindPort( ports, "PORT2" );
  inst->bitsig  = mti_FindPort( ports, "p1" );
  inst->realsig = mti_FindPort( ports, "rPort" );

  inst->procid = mti_CreateProcess( "ValueChecker", checkValues, inst );

  mti_AddQuitCB( cleanupCallback, inst );
  mti_AddRestartCB( cleanupCallback, inst );
} 

HDL code

entity for_model is
  port ( p1    : bit;
         port2 : integer;
         rport : real
       );
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

entity top is
end top;

architecture a of top is

  signal s1 : bit := '0';
  signal s2 : integer := 42;
  signal s3 : real := 1.57;

  component for_model is
    port ( p1    : bit;
           port2 : integer;
           rport : real
         );
  end component;

  for all : for_model use entity work.for_model(a);

begin
  i1 : for_model
       port map ( s1, s2, s3 );

  s1 <= not s1 after 5 ns;
  s2 <= s2 + 1 after 5 ns;
  s3 <= s3 + 1.5 after 5 ns;
end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 15
# Time [0,0] delta 0:
#   s1 = 0
#   s2 = 42
#   s3 = 1.57
# Time [0,5] delta 0:
#   s1 = 1
#   s2 = 43
#   s3 = 3.07
# Time [0,10] delta 0:
#   s1 = 0
#   s2 = 44
#   s3 = 4.57
# Time [0,15] delta 0:
#   s1 = 1
#   s2 = 45
#   s3 = 6.07
VSIM 2> quit
# Cleaning up... 

Note: mti_GetSignalName() returns the name of the top-level signal connected to each port because of standard simulator optimization that collapses hierarchical port connections wherever possible.

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