mti_FindDriver()

Determines if a VHDL signal has any drivers on it.

Syntax

driver_id = mti_FindDriver( signal_id ) 

Returns

Name	Type	Description
driver_id	mtiDriverIdT	A handle to a driver of the specified signal or NULL if there is an error, if no drivers are found for a scalar signal, or if any element of an array signal does not have a driver

Arguments

Name	Type	Description
signal_id	mtiSignalIdT	A handle to the VHDL signal

Description

mti_FindDriver() returns a handle to a driver of the specified signal. If no drivers are found for a scalar signal or if any element of an array signal does not have a driver, then NULL is returned. The returned handle can be freed with mti_Free(). The driver remains in effect even if the handle is freed.

Related functions

mti_CreateDriver()

mti_GetDriverSubelements()

Example

FLI code

#include <mti.h>

void loadDoneCB( void * param )
{
  mtiDriverIdT  drvid;
  mtiSignalIdT  sigid;

  sigid = mti_FindSignal( "/top/s1" );
  drvid = mti_FindDriver( sigid );
  mti_PrintFormatted( "Driver %sfound for /top/s1\n", drvid ? "" : "not " );

  sigid = mti_FindSignal( "/top/s2" );
  drvid = mti_FindDriver( sigid );
  mti_PrintFormatted( "Driver %sfound for /top/s2\n", drvid ? "" : "not " );

  sigid = mti_FindSignal( "/top/s3" );
  drvid = mti_FindDriver( sigid );
  mti_PrintFormatted( "Driver %sfound for /top/s3\n", drvid ? "" : "not " );

  sigid = mti_FindSignal( "/top/s4" );
  drvid = mti_FindDriver( sigid );
  mti_PrintFormatted( "Driver %sfound for /top/s4\n", drvid ? "" : "not " );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mti_AddLoadDoneCB( loadDoneCB, 0 );
} 

HDL code

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal s1 : std_logic := '0';
  signal s2 : std_logic := '0';
  signal s3 : std_logic_vector( 3 downto 0 ) := "0110";
  signal s4 : std_logic_vector( 3 downto 0 ) := "1010";

begin

  s4 <= not s4 after 5 ns;

  p1 : process
  begin
    c1 : case s1 is
      when 'U' => s1 <= 'X' after 5 ns;
      when 'X' => s1 <= '0' after 5 ns;
      when '0' => s1 <= '1' after 5 ns;
      when '1' => s1 <= 'Z' after 5 ns;
      when 'Z' => s1 <= 'W' after 5 ns;
      when 'W' => s1 <= 'L' after 5 ns;
      when 'L' => s1 <= 'H' after 5 ns;
      when 'H' => s1 <= '-' after 5 ns;
      when '-' => s1 <= 'U' after 5 ns;
    end case c1;
    s3(3) <= not s3(3) after 5 ns;
    wait for 5 ns;
  end process;

end a; 

Simulation output

% vsim -c top -foreign "initForeign for_model.sl"
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -foreign {initForeign for_model.sl} -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading ./for_model.sl
# Driver found for /top/s1
# Driver not found for /top/s2
# Driver not found for /top/s3
# Driver found for /top/s4
VSIM 1> run 10
VSIM 2> quit 

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