mti_FatalError()

Requests the simulator to halt with a fatal error.

Syntax

mti_FatalError() 

Returns

Nothing

Arguments

None

Description

mti_FatalError() causes the simulator to immediately halt the simulation and issue an assertion message with the text "** Fatal: Foreign module requested halt". A call to mti_FatalError() does not return control to the caller. The simulation cannot be continued after being halted with mti_FatalError().

Related functions

mti_Break()

mti_Quit()

Example

FLI code

#include <mti.h>

typedef enum {
  STD_LOGIC_U,      /* 'U' */
  STD_LOGIC_X,      /* 'X' */
  STD_LOGIC_0,      /* '0' */
  STD_LOGIC_1,      /* '1' */
  STD_LOGIC_Z,      /* 'Z' */
  STD_LOGIC_W,      /* 'W' */
  STD_LOGIC_L,      /* 'L' */
  STD_LOGIC_H,      /* 'H' */
  STD_LOGIC_D       /* '-' */
} StdLogicT;

void monitorSignal( void * param )
{
  mtiSignalIdT sigid = (mtiSignalIdT)param;

  switch ( mti_GetSignalValue( sigid ) ) {
    case STD_LOGIC_X:
    case STD_LOGIC_W:
        mti_PrintFormatted( "Time [%d,%d] delta %d: Signal %s is UNKNOWN\n",
                           mti_NowUpper(), mti_Now(), mti_Delta(),
                           mti_GetSignalName( sigid ) );
        mti_FatalError();
        break;
    default:
        break;
  }
}
void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  mtiProcessIdT procid;
  mtiSignalIdT  sigid;

  sigid  = mti_FindSignal( "/top/s1" );
  procid = mti_CreateProcess( "SignalMonitor", monitorSignal, sigid );
  mti_Sensitize( procid, sigid, MTI_EVENT );
} 

HDL code

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal s1 : std_logic := '0';

begin

  p1 : process
  begin
    c1 : case s1 is
      when 'U' => s1 <= 'X' after 5 ns;
      when 'X' => s1 <= '0' after 5 ns;
      when '0' => s1 <= '1' after 5 ns;
      when '1' => s1 <= 'Z' after 5 ns;
      when 'Z' => s1 <= 'W' after 5 ns;
      when 'W' => s1 <= 'L' after 5 ns;
      when 'L' => s1 <= 'H' after 5 ns;
      when 'H' => s1 <= '-' after 5 ns;
      when '-' => s1 <= 'U' after 5 ns;
    end case c1;
    wait for 5 ns;
  end process;

end a; 

Simulation output

% vsim -c top -foreign "initForeign for_model.sl"
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -foreign {initForeign for_model.sl} -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading ./for_model.sl
VSIM 1> run 20
# Time [0,15] delta 0: Signal s1 is UNKNOWN
# ** Fatal: Foreign module requested halt
#    Time: 15 ns  Iteration: 0  Instance: /top
# Fatal error at  line 0
# 
VSIM 2> cont
# Cannot continue because of fatal error.
VSIM 3> quit 

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