mti_Desensitize()

Desensitizes a VHDL process to the VHDL signals to which it is sensitive.

Syntax

mti_Desensitize( proc ) 

Returns

Nothing

Arguments

Name	Type	Description
proc	mtiProcessIdT	A handle to a VHDL process

Description

mti_Desensitize() disconnects a process from the signals to which it is sensitive. The process can then be resensitized (mti_Sensitize()) or scheduled (mti_ScheduleWakeup()).

Related functions

mti_ScheduleWakeup()

mti_Sensitize()

Example

FLI code

#include <stdlib.h>
#include <mti.h>

typedef enum {
  STD_LOGIC_U,
  STD_LOGIC_X,
  STD_LOGIC_0,
  STD_LOGIC_1,
  STD_LOGIC_Z,
  STD_LOGIC_W,
  STD_LOGIC_L,
  STD_LOGIC_H,
  STD_LOGIC_D
} standardLogicType;

typedef struct {
  mtiSignalIdT  sigid;
  mtiProcessIdT procid;
} instanceInfoT;

char * convertStdLogicValue( mtiInt32T sigval )
{
  char * retval;

  switch ( sigval ) {
    case STD_LOGIC_U:  retval = "'U'";  break;
    case STD_LOGIC_X:  retval = "'X'";  break;
    case STD_LOGIC_0:  retval = "'0'";  break;
    case STD_LOGIC_1:  retval = "'1'";  break;
    case STD_LOGIC_Z:  retval = "'Z'";  break;
    case STD_LOGIC_W:  retval = "'W'";  break;
    case STD_LOGIC_L:  retval = "'L'";  break;
    case STD_LOGIC_H:  retval = "'H'";  break;
    case STD_LOGIC_D:  retval = "'-'";  break;
    default:  retval = "?";  break;
  }
  return retval;
}

void monitorSignal( void * param )
{
  char          * region_name;
  instanceInfoT * inst = (instanceInfoT*)param;
  mtiInt32T       sigval;

  region_name = mti_GetRegionFullName( mti_GetSignalRegion( inst->sigid ) );
  sigval = mti_GetSignalValue( inst->sigid );
  mti_PrintFormatted( "Time [%d,%d] delta %d: Signal %s/%s is %s\n",
                     mti_NowUpper(), mti_Now(), mti_Delta(),
                     region_name, mti_GetSignalName( inst->sigid ),
                     convertStdLogicValue( sigval ) );
  if ( mti_Now() >= 20 ) {
      mti_PrintFormatted( "  Desensitizing process %s\n",
                         mti_GetProcessName( inst->procid ) );
      mti_Desensitize( inst->procid );
  }
  mti_VsimFree( region_name );
}

void cleanupCallback( void * param )
{
  mti_PrintMessage( "Cleaning up...\n" );
  free( param );
}

void initForeign(
  mtiRegionIdT       region,   /* The ID of the region in which this     */
                               /* foreign architecture is instantiated.  */
  char              *param,    /* The last part of the string in the     */
                               /* foreign attribute.                     */
  mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/
  mtiInterfaceListT *ports     /* A list of ports for the foreign model.   */
)
{
  instanceInfoT * inst;

  inst         = (instanceInfoT *)malloc( sizeof(instanceInfoT) );
  inst->sigid  = mti_FindSignal( "/top/s1" );
  inst->procid = mti_CreateProcess( "sigMonitor", monitorSignal,inst );
  mti_Sensitize( inst->procid, inst->sigid, MTI_EVENT );
  mti_AddQuitCB( cleanupCallback, inst );
  mti_AddRestartCB( cleanupCallback, inst );
} 

HDL code

entity for_model is
end for_model;

architecture a of for_model is
  attribute foreign of a : architecture is "initForeign for_model.sl";
begin
end a;

library ieee;
use ieee.std_logic_1164.all;

entity top is
end top;

architecture a of top is

  signal s1 : std_logic := '0';

  component for_model is
  end component;

  for all : for_model use entity work.for_model(a);

begin

  i1 : for_model;

  p1 : process
  begin
    s1 <= '1';
    wait for 5 ns;
    s1 <= '0';
    wait for 0 ns;
    s1 <= '1';
    wait for 0 ns;
    s1 <= '0';
    wait for 5 ns;
  end process;

end a; 

Simulation output

% vsim -c top
Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl 

# 5.4b

# vsim -c top 
# Loading .../modeltech/sunos5/../std.standard
# Loading .../modeltech/sunos5/../ieee.std_logic_1164(body)
# Loading work.top(a)
# Loading work.for_model(a)
# Loading ./for_model.sl
VSIM 1> run 30
# Time [0,0] delta 0: Signal /top/s1 is '0'
# Time [0,0] delta 1: Signal /top/s1 is '1'
# Time [0,5] delta 1: Signal /top/s1 is '0'
# Time [0,5] delta 2: Signal /top/s1 is '1'
# Time [0,5] delta 3: Signal /top/s1 is '0'
# Time [0,10] delta 1: Signal /top/s1 is '1'
# Time [0,15] delta 1: Signal /top/s1 is '0'
# Time [0,15] delta 2: Signal /top/s1 is '1'
# Time [0,15] delta 3: Signal /top/s1 is '0'
# Time [0,20] delta 1: Signal /top/s1 is '1'
#   Desensitizing process sigMonitor
VSIM 2> run 10
VSIM 3> quit
# Cleaning up... 

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