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mti_ScheduleWakeup()
Schedules a VHDL process to wake up at a specific time.
Syntax
mti_ScheduleWakeup( process_id, delay )Returns
Arguments
Name Type Description process_id mtiProcessIdT A handle to a VHDL process delay mtiDelayT The delay to be used in current simulator time unitsDescription
mti_ScheduleWakeup() schedules the specified process to be called after the specified delay. A process can have no more than one pending wake-up call. A call to mti_ScheduleWakeup() cancels a prior pending wake-up call for the specified process regardless of the delay values. The delay time units are equivalent to the current simulator time unit setting.
Related functions
Example
FLI code
#include <stdlib.h> #include <mti.h> typedef struct { mtiDelayT delay; mtiProcessIdT procid; mtiSignalIdT i1_sigid; mtiSignalIdT t1_sigid; mtiDriverIdT i1_drvid; mtiDriverIdT t1_drvid; long i1_last_value; long t1_last_value; } instanceInfoT; static long invertBit( long value ) { if ( value == 0 ) { return 1; } else { return 0; } } void driveSignal( instanceInfoT * inst ) { inst->i1_last_value = invertBit( inst->i1_last_value ); mti_ScheduleDriver( inst->i1_drvid, inst->i1_last_value, 5, MTI_INERTIAL ); inst->t1_last_value = invertBit( inst->t1_last_value ); mti_ScheduleDriver( inst->t1_drvid, inst->t1_last_value, 5, MTI_TRANSPORT ); mti_ScheduleWakeup( inst->procid, inst->delay ); inst->delay++; } void cleanupCallback( void * param ) { mti_PrintMessage( "Cleaning up...\n" ); free( param ); } void loadDoneCallback( instanceInfoT * inst ) { inst->i1_last_value = mti_GetSignalValue( inst->i1_sigid ); inst->t1_last_value = mti_GetSignalValue( inst->t1_sigid ); } void initForeign( mtiRegionIdT region, /* The ID of the region in which this */ /* foreign architecture is instantiated. */ char *param, /* The last part of the string in the */ /* foreign attribute. */ mtiInterfaceListT *generics, /* A list of generics for the foreign model.*/ mtiInterfaceListT *ports /* A list of ports for the foreign model. */ ) { instanceInfoT * inst; inst = (instanceInfoT *)malloc( sizeof(instanceInfoT) ); inst->procid = mti_CreateProcess( "SignalDriver", driveSignal, inst ); inst->delay = 1; mti_ScheduleWakeup( inst->procid, inst->delay ); inst->i1_sigid = mti_FindSignal( "/top/i1" ); inst->i1_drvid = mti_CreateDriver( inst->i1_sigid ); mti_SetDriverOwner( inst->i1_drvid, inst->procid ); inst->t1_sigid = mti_FindSignal( "/top/t1" ); inst->t1_drvid = mti_CreateDriver( inst->t1_sigid ); mti_SetDriverOwner( inst->t1_drvid, inst->procid ); mti_AddLoadDoneCB( loadDoneCallback, inst ); mti_AddQuitCB( cleanupCallback, inst ); mti_AddRestartCB( cleanupCallback, inst ); }HDL code
entity for_model is end for_model; architecture a of for_model is attribute foreign of a : architecture is "initForeign for_model.sl;"; begin end a; entity top is end top; architecture a of top is signal i1 : bit := '0'; signal t1 : bit := '0'; component for_model end component; begin forinst : for_model; end a;Simulation output
% vsim -c top Reading .../modeltech/sunos5/../tcl/vsim/pref.tcl # 5.4b # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl VSIM 1> add list /top/i1 /top/t1 VSIM 2> run 35 VSIM 3> write list list.out VSIM 4> quit # Cleaning up... % cat list.out ns /top/i1 delta /top/t1 0 +0 0 0 5 +0 0 1 6 +0 0 0 8 +0 0 1 11 +0 0 0 15 +0 1 1 20 +0 0 0 26 +0 1 1 33 +0 0 0
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